//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.const .align 4 .b8 kNTSCColorBars[396] = {195, 245, 40, 63, 42, 58, 18, 62, 0, 0, 64, 63, 0, 0, 64, 63, 0, 0, 64, 63, 69, 71, 146, 62, 0, 0, 0, 0, 0, 0, 64, 63, 0, 0, 64, 63, 118, 113, 219, 62, 0, 0, 64, 63, 0, 0, 64, 63, 0, 0, 0, 0, 69, 71, 18, 63, 0, 0, 0, 0, 0, 0, 64, 63, 0, 0, 0, 0, 93, 220, 54, 63, 0, 0, 64, 63, 0, 0, 0, 0, 0, 0, 64, 63, 232, 106, 91, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 63, 0, 0, 128, 63, 0, 0, 64, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 63, 42, 58, 18, 62, 0, 0, 64, 63, 0, 0, 0, 0, 0, 0, 0, 0, 69, 71, 146, 62, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 118, 113, 219, 62, 0, 0, 64, 63, 0, 0, 0, 0, 0, 0, 64, 63, 69, 71, 18, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 93, 220, 54, 63, 0, 0, 64, 63, 0, 0, 64, 63, 0, 0, 0, 0, 232, 106, 91, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 128, 63, 0, 0, 64, 63, 0, 0, 64, 63, 0, 0, 64, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 128, 63, 235, 226, 54, 62, 15, 156, 211, 62, 18, 165, 125, 62, 224, 45, 16, 187, 208, 213, 182, 62, 0, 0, 128, 63, 0, 0, 128, 63, 0, 0, 128, 63, 48, 42, 9, 63, 178, 157, 239, 62, 108, 9, 249, 186, 55, 137, 129, 62, 235, 226, 54, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 193, 57, 67, 63, 10, 215, 35, 189, 10, 215, 35, 189, 10, 215, 35, 189, 100, 59, 79, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 232, 106, 91, 63, 10, 215, 35, 61, 10, 215, 35, 61, 10, 215, 35, 61, 0, 0, 128, 63, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};

.visible .entry ColorBarsKernelCuda(
	.param .u64 ColorBarsKernelCuda_param_0,
	.param .u32 ColorBarsKernelCuda_param_1,
	.param .u32 ColorBarsKernelCuda_param_2,
	.param .u32 ColorBarsKernelCuda_param_3,
	.param .u32 ColorBarsKernelCuda_param_4
)
{
	.reg .pred 	%p<7>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<22>;
	.reg .f32 	%f<18>;
	.reg .s64 	%rd<18>;


	ld.param.u64 	%rd5, [ColorBarsKernelCuda_param_0];
	ld.param.u32 	%r7, [ColorBarsKernelCuda_param_1];
	ld.param.u32 	%r8, [ColorBarsKernelCuda_param_2];
	ld.param.u32 	%r9, [ColorBarsKernelCuda_param_3];
	ld.param.u32 	%r10, [ColorBarsKernelCuda_param_4];
	cvta.to.global.u64 	%rd1, %rd5;
	mov.u32 	%r11, %ntid.x;
	mov.u32 	%r12, %ctaid.x;
	mov.u32 	%r13, %tid.x;
	mad.lo.s32 	%r1, %r11, %r12, %r13;
	mov.u32 	%r14, %ntid.y;
	mov.u32 	%r15, %ctaid.y;
	mov.u32 	%r16, %tid.y;
	mad.lo.s32 	%r2, %r14, %r15, %r16;
	setp.lt.s32	%p1, %r1, %r9;
	setp.lt.s32	%p2, %r2, %r10;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_8;
	bra.uni 	BB0_1;

BB0_1:
	cvt.rn.f32.s32	%f6, %r1;
	add.ftz.f32 	%f7, %f6, 0f3F7D70A4;
	cvt.rn.f32.s32	%f8, %r9;
	div.approx.ftz.f32 	%f9, %f7, %f8;
	cvt.ftz.sat.f32.f32	%f1, %f9;
	cvt.rn.f32.s32	%f10, %r2;
	add.ftz.f32 	%f11, %f10, 0f3F7D70A4;
	cvt.rn.f32.s32	%f12, %r10;
	div.approx.ftz.f32 	%f13, %f11, %f12;
	cvt.ftz.sat.f32.f32	%f2, %f13;
	mov.u32 	%r20, 0;

BB0_2:
	cvt.s64.s32	%rd2, %r20;
	mul.wide.s32 	%rd6, %r20, 132;
	mov.u64 	%rd7, kNTSCColorBars;
	add.s64 	%rd8, %rd7, %rd6;
	ld.const.f32 	%f14, [%rd8];
	setp.gt.ftz.f32	%p4, %f2, %f14;
	add.s32 	%r20, %r20, 1;
	@%p4 bra 	BB0_2;

	mov.u32 	%r21, 0;
	mul.lo.s64 	%rd9, %rd2, 132;

BB0_4:
	add.s64 	%rd11, %rd7, %rd9;
	mul.wide.s32 	%rd12, %r21, 16;
	add.s64 	%rd13, %rd11, %rd12;
	add.s64 	%rd3, %rd13, 4;
	ld.const.f32 	%f15, [%rd13+4];
	setp.gt.ftz.f32	%p5, %f1, %f15;
	add.s32 	%r21, %r21, 1;
	@%p5 bra 	BB0_4;

	ld.const.f32 	%f3, [%rd3+4];
	ld.const.f32 	%f4, [%rd3+8];
	ld.const.f32 	%f5, [%rd3+12];
	mad.lo.s32 	%r19, %r2, %r7, %r1;
	cvt.s64.s32	%rd4, %r19;
	setp.eq.s32	%p6, %r8, 0;
	@%p6 bra 	BB0_7;

	shl.b64 	%rd14, %rd4, 4;
	add.s64 	%rd15, %rd1, %rd14;
	mov.f32 	%f16, 0f3F800000;
	st.global.v4.f32 	[%rd15], {%f3, %f4, %f5, %f16};
	bra.uni 	BB0_8;

BB0_7:
	shl.b64 	%rd16, %rd4, 3;
	add.s64 	%rd17, %rd1, %rd16;
	mov.f32 	%f17, 0f3F800000;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f17;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f5;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f4;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f3;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd17], {%rs4, %rs3, %rs2, %rs1};

BB0_8:
	ret;
}


