//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;
// ShaderKernel_ASCCombined$__cuda_local_var_180676_471_non_const_p_local has been demoted

.visible .entry ShaderKernel_ASCCombined(
	.param .u64 ShaderKernel_ASCCombined_param_0,
	.param .u32 ShaderKernel_ASCCombined_param_1,
	.param .u32 ShaderKernel_ASCCombined_param_2,
	.param .u32 ShaderKernel_ASCCombined_param_3,
	.param .u32 ShaderKernel_ASCCombined_param_4,
	.param .u64 ShaderKernel_ASCCombined_param_5,
	.param .u64 ShaderKernel_ASCCombined_param_6
)
{
	.reg .pred 	%p<12>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<89>;
	.reg .s64 	%rd<16>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_ASCCombined$__cuda_local_var_180676_471_non_const_p_local[64];

	ld.param.u64 	%rd2, [ShaderKernel_ASCCombined_param_0];
	ld.param.u32 	%r4, [ShaderKernel_ASCCombined_param_1];
	ld.param.u32 	%r5, [ShaderKernel_ASCCombined_param_2];
	ld.param.u32 	%r6, [ShaderKernel_ASCCombined_param_3];
	ld.param.u32 	%r7, [ShaderKernel_ASCCombined_param_4];
	ld.param.u64 	%rd3, [ShaderKernel_ASCCombined_param_5];
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_15;
	bra.uni 	BB0_1;

BB0_1:
	setp.gt.u32	%p4, %r1, 3;
	@%p4 bra 	BB0_3;

	cvta.to.global.u64 	%rd4, %rd3;
	mul.wide.u32 	%rd5, %r1, 16;
	mov.u64 	%rd6, ShaderKernel_ASCCombined$__cuda_local_var_180676_471_non_const_p_local;
	add.s64 	%rd7, %rd6, %rd5;
	add.s64 	%rd8, %rd4, %rd5;
	ld.global.v4.f32 	{%f23, %f24, %f25, %f26}, [%rd8];
	st.shared.v4.f32 	[%rd7], {%f23, %f24, %f25, %f26};

BB0_3:
	cvt.rn.f32.s32	%f31, %r2;
	add.ftz.f32 	%f1, %f31, 0f3F000000;
	cvt.rn.f32.s32	%f32, %r3;
	add.ftz.f32 	%f2, %f32, 0f3F000000;
	bar.sync 	0;
	// inline asm
	tex.2d.v4.f32.f32 {%f33, %f34, %f35, %f36}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	ld.shared.v4.f32 	{%f39, %f40, %f41, %f42}, [ShaderKernel_ASCCombined$__cuda_local_var_180676_471_non_const_p_local];
	ld.shared.v4.f32 	{%f43, %f44, %f45, %f46}, [ShaderKernel_ASCCombined$__cuda_local_var_180676_471_non_const_p_local+16];
	fma.rn.ftz.f32 	%f7, %f35, %f39, %f43;
	fma.rn.ftz.f32 	%f8, %f34, %f40, %f44;
	fma.rn.ftz.f32 	%f9, %f33, %f41, %f45;
	abs.ftz.f32 	%f10, %f7;
	abs.ftz.f32 	%f11, %f8;
	abs.ftz.f32 	%f12, %f9;
	setp.gtu.ftz.f32	%p5, %f10, 0f00000000;
	@%p5 bra 	BB0_5;

	mov.f32 	%f86, 0f00000000;
	bra.uni 	BB0_6;

BB0_5:
	ld.shared.f32 	%f54, [ShaderKernel_ASCCombined$__cuda_local_var_180676_471_non_const_p_local+32];
	lg2.approx.ftz.f32 	%f55, %f10;
	mul.ftz.f32 	%f56, %f55, %f54;
	ex2.approx.ftz.f32 	%f86, %f56;

BB0_6:
	setp.gtu.ftz.f32	%p6, %f11, 0f00000000;
	@%p6 bra 	BB0_8;

	mov.f32 	%f87, 0f00000000;
	bra.uni 	BB0_9;

BB0_8:
	ld.shared.f32 	%f58, [ShaderKernel_ASCCombined$__cuda_local_var_180676_471_non_const_p_local+36];
	lg2.approx.ftz.f32 	%f59, %f11;
	mul.ftz.f32 	%f60, %f59, %f58;
	ex2.approx.ftz.f32 	%f87, %f60;

BB0_9:
	setp.gtu.ftz.f32	%p7, %f12, 0f00000000;
	@%p7 bra 	BB0_11;

	mov.f32 	%f88, 0f00000000;
	bra.uni 	BB0_12;

BB0_11:
	ld.shared.f32 	%f62, [ShaderKernel_ASCCombined$__cuda_local_var_180676_471_non_const_p_local+40];
	lg2.approx.ftz.f32 	%f63, %f12;
	mul.ftz.f32 	%f64, %f63, %f62;
	ex2.approx.ftz.f32 	%f88, %f64;

BB0_12:
	setp.lt.ftz.f32	%p8, %f7, 0f00000000;
	selp.f32	%f65, 0fBF800000, 0f3F800000, %p8;
	setp.lt.ftz.f32	%p9, %f8, 0f00000000;
	selp.f32	%f66, 0fBF800000, 0f3F800000, %p9;
	setp.lt.ftz.f32	%p10, %f9, 0f00000000;
	selp.f32	%f67, 0fBF800000, 0f3F800000, %p10;
	mul.ftz.f32 	%f68, %f86, %f65;
	mul.ftz.f32 	%f69, %f87, %f66;
	mul.ftz.f32 	%f70, %f69, 0f3F371759;
	fma.rn.ftz.f32 	%f71, %f68, 0f3E59B3D0, %f70;
	mul.ftz.f32 	%f72, %f88, %f67;
	fma.rn.ftz.f32 	%f73, %f72, 0f3D93DD98, %f71;
	sub.ftz.f32 	%f74, %f68, %f73;
	sub.ftz.f32 	%f75, %f69, %f73;
	sub.ftz.f32 	%f76, %f72, %f73;
	ld.shared.v4.f32 	{%f77, %f78, %f79, %f80}, [ShaderKernel_ASCCombined$__cuda_local_var_180676_471_non_const_p_local+48];
	fma.rn.ftz.f32 	%f19, %f74, %f77, %f73;
	fma.rn.ftz.f32 	%f20, %f75, %f78, %f73;
	fma.rn.ftz.f32 	%f21, %f76, %f79, %f73;
	add.ftz.f32 	%f84, %f36, 0f80000000;
	fma.rn.ftz.f32 	%f22, %f84, %f80, 0f00000000;
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	cvt.s64.s32	%rd1, %r13;
	setp.eq.s32	%p11, %r5, 0;
	@%p11 bra 	BB0_14;

	cvta.to.global.u64 	%rd10, %rd2;
	shl.b64 	%rd11, %rd1, 4;
	add.s64 	%rd12, %rd10, %rd11;
	st.global.v4.f32 	[%rd12], {%f21, %f20, %f19, %f22};
	bra.uni 	BB0_15;

BB0_14:
	cvta.to.global.u64 	%rd13, %rd2;
	shl.b64 	%rd14, %rd1, 3;
	add.s64 	%rd15, %rd13, %rd14;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f22;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f19;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f20;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f21;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd15], {%rs4, %rs3, %rs2, %rs1};

BB0_15:
	ret;
}


