//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64


.visible .func  (.param .align 16 .b8 func_retval0[16]) _Z18UnpremultiplyPixel8PixelRGB(
	.param .align 16 .b8 _Z18UnpremultiplyPixel8PixelRGB_param_0[16]
)
{
	.reg .pred 	%p<2>;
	.reg .f32 	%f<24>;


	ld.param.f32 	%f11, [_Z18UnpremultiplyPixel8PixelRGB_param_0+8];
	ld.param.f32 	%f10, [_Z18UnpremultiplyPixel8PixelRGB_param_0+4];
	ld.param.f32 	%f9, [_Z18UnpremultiplyPixel8PixelRGB_param_0];
	ld.param.f32 	%f12, [_Z18UnpremultiplyPixel8PixelRGB_param_0+12];
	cvt.ftz.sat.f32.f32	%f20, %f12;
	add.ftz.f32 	%f13, %f20, 0fB70637BD;
	setp.gtu.ftz.f32	%p1, %f13, 0f00000000;
	@%p1 bra 	BB0_2;

	mov.f32 	%f23, 0f00000000;
	mov.f32 	%f22, %f23;
	mov.f32 	%f21, %f23;
	mov.f32 	%f20, %f23;
	bra.uni 	BB0_3;

BB0_2:
	mov.f32 	%f18, 0f3F800000;
	div.approx.ftz.f32 	%f19, %f18, %f20;
	mul.ftz.f32 	%f21, %f11, %f19;
	mul.ftz.f32 	%f22, %f10, %f19;
	mul.ftz.f32 	%f23, %f9, %f19;

BB0_3:
	st.param.f32	[func_retval0+0], %f23;
	st.param.f32	[func_retval0+4], %f22;
	st.param.f32	[func_retval0+8], %f21;
	st.param.f32	[func_retval0+12], %f20;
	ret;
}

.visible .entry AlphaGainKernel(
	.param .u64 AlphaGainKernel_param_0,
	.param .u32 AlphaGainKernel_param_1,
	.param .u64 AlphaGainKernel_param_2,
	.param .u32 AlphaGainKernel_param_3,
	.param .u32 AlphaGainKernel_param_4,
	.param .u32 AlphaGainKernel_param_5,
	.param .u32 AlphaGainKernel_param_6,
	.param .f32 AlphaGainKernel_param_7
)
{
	.reg .pred 	%p<6>;
	.reg .s16 	%rs<13>;
	.reg .s32 	%r<16>;
	.reg .f32 	%f<23>;
	.reg .s64 	%rd<15>;


	ld.param.u64 	%rd5, [AlphaGainKernel_param_0];
	ld.param.u32 	%r3, [AlphaGainKernel_param_1];
	ld.param.u64 	%rd6, [AlphaGainKernel_param_2];
	ld.param.u32 	%r4, [AlphaGainKernel_param_3];
	ld.param.u32 	%r5, [AlphaGainKernel_param_4];
	ld.param.u32 	%r6, [AlphaGainKernel_param_5];
	ld.param.u32 	%r7, [AlphaGainKernel_param_6];
	ld.param.f32 	%f14, [AlphaGainKernel_param_7];
	cvta.to.global.u64 	%rd1, %rd6;
	cvta.to.global.u64 	%rd2, %rd5;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r10, %tid.x;
	mad.lo.s32 	%r1, %r8, %r9, %r10;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r2, %r11, %r12, %r13;
	setp.lt.s32	%p1, %r1, %r6;
	setp.lt.s32	%p2, %r2, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB1_7;
	bra.uni 	BB1_1;

BB1_1:
	mad.lo.s32 	%r14, %r2, %r3, %r1;
	cvt.s64.s32	%rd3, %r14;
	setp.eq.s32	%p4, %r5, 0;
	@%p4 bra 	BB1_3;

	shl.b64 	%rd7, %rd3, 4;
	add.s64 	%rd8, %rd2, %rd7;
	ld.global.v4.f32 	{%f15, %f16, %f17, %f18}, [%rd8];
	mov.f32 	%f22, %f18;
	mov.f32 	%f21, %f17;
	mov.f32 	%f20, %f16;
	mov.f32 	%f19, %f15;
	bra.uni 	BB1_4;

BB1_3:
	shl.b64 	%rd9, %rd3, 3;
	add.s64 	%rd10, %rd2, %rd9;
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd10];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f19, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f20, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f21, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f22, %temp;
	}

BB1_4:
	mul.ftz.f32 	%f13, %f22, %f14;
	mad.lo.s32 	%r15, %r2, %r4, %r1;
	cvt.s64.s32	%rd4, %r15;
	@%p4 bra 	BB1_6;

	shl.b64 	%rd11, %rd4, 4;
	add.s64 	%rd12, %rd1, %rd11;
	st.global.v4.f32 	[%rd12], {%f19, %f20, %f21, %f13};
	bra.uni 	BB1_7;

BB1_6:
	shl.b64 	%rd13, %rd4, 3;
	add.s64 	%rd14, %rd1, %rd13;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f13;
	mov.b16 	%rs9, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f19;
	mov.b16 	%rs10, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f20;
	mov.b16 	%rs11, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f21;
	mov.b16 	%rs12, %temp;
}
	st.global.v4.u16 	[%rd14], {%rs10, %rs11, %rs12, %rs9};

BB1_7:
	ret;
}

.visible .entry UnpremultiplyKernel(
	.param .u64 UnpremultiplyKernel_param_0,
	.param .u32 UnpremultiplyKernel_param_1,
	.param .u64 UnpremultiplyKernel_param_2,
	.param .u32 UnpremultiplyKernel_param_3,
	.param .u32 UnpremultiplyKernel_param_4,
	.param .u32 UnpremultiplyKernel_param_5,
	.param .u32 UnpremultiplyKernel_param_6,
	.param .align 16 .b8 UnpremultiplyKernel_param_7[16]
)
{
	.reg .pred 	%p<7>;
	.reg .s16 	%rs<13>;
	.reg .s32 	%r<16>;
	.reg .f32 	%f<54>;
	.reg .s64 	%rd<15>;


	ld.param.u64 	%rd5, [UnpremultiplyKernel_param_0];
	ld.param.u32 	%r3, [UnpremultiplyKernel_param_1];
	ld.param.u64 	%rd6, [UnpremultiplyKernel_param_2];
	ld.param.u32 	%r4, [UnpremultiplyKernel_param_3];
	ld.param.u32 	%r5, [UnpremultiplyKernel_param_4];
	ld.param.u32 	%r6, [UnpremultiplyKernel_param_5];
	ld.param.u32 	%r7, [UnpremultiplyKernel_param_6];
	ld.param.f32 	%f23, [UnpremultiplyKernel_param_7+8];
	ld.param.f32 	%f22, [UnpremultiplyKernel_param_7+4];
	ld.param.f32 	%f21, [UnpremultiplyKernel_param_7];
	cvta.to.global.u64 	%rd1, %rd6;
	cvta.to.global.u64 	%rd2, %rd5;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r10, %tid.x;
	mad.lo.s32 	%r1, %r8, %r9, %r10;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r2, %r11, %r12, %r13;
	setp.lt.s32	%p1, %r1, %r6;
	setp.lt.s32	%p2, %r2, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB2_10;
	bra.uni 	BB2_1;

BB2_1:
	mad.lo.s32 	%r14, %r2, %r3, %r1;
	cvt.s64.s32	%rd3, %r14;
	setp.eq.s32	%p4, %r5, 0;
	@%p4 bra 	BB2_3;

	shl.b64 	%rd7, %rd3, 4;
	add.s64 	%rd8, %rd2, %rd7;
	ld.global.v4.f32 	{%f25, %f26, %f27, %f28}, [%rd8];
	mov.f32 	%f49, %f28;
	mov.f32 	%f48, %f27;
	mov.f32 	%f47, %f26;
	mov.f32 	%f46, %f25;
	bra.uni 	BB2_4;

BB2_3:
	shl.b64 	%rd9, %rd3, 3;
	add.s64 	%rd10, %rd2, %rd9;
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd10];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f46, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f47, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f48, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f49, %temp;
	}

BB2_4:
	cvt.ftz.sat.f32.f32	%f50, %f49;
	add.ftz.f32 	%f29, %f50, 0fB70637BD;
	setp.gtu.ftz.f32	%p5, %f29, 0f00000000;
	@%p5 bra 	BB2_6;

	mov.f32 	%f53, 0f00000000;
	mov.f32 	%f52, %f53;
	mov.f32 	%f51, %f53;
	mov.f32 	%f50, %f53;
	bra.uni 	BB2_7;

BB2_6:
	mov.f32 	%f34, 0f3F800000;
	sub.ftz.f32 	%f35, %f34, %f50;
	mul.ftz.f32 	%f36, %f23, %f35;
	mul.ftz.f32 	%f37, %f22, %f35;
	mul.ftz.f32 	%f38, %f21, %f35;
	sub.ftz.f32 	%f39, %f46, %f38;
	cvt.ftz.sat.f32.f32	%f40, %f39;
	sub.ftz.f32 	%f41, %f47, %f37;
	cvt.ftz.sat.f32.f32	%f42, %f41;
	sub.ftz.f32 	%f43, %f48, %f36;
	cvt.ftz.sat.f32.f32	%f44, %f43;
	div.approx.ftz.f32 	%f45, %f34, %f50;
	mul.ftz.f32 	%f51, %f44, %f45;
	mul.ftz.f32 	%f52, %f42, %f45;
	mul.ftz.f32 	%f53, %f40, %f45;

BB2_7:
	mad.lo.s32 	%r15, %r2, %r4, %r1;
	cvt.s64.s32	%rd4, %r15;
	@%p4 bra 	BB2_9;

	shl.b64 	%rd11, %rd4, 4;
	add.s64 	%rd12, %rd1, %rd11;
	st.global.v4.f32 	[%rd12], {%f53, %f52, %f51, %f50};
	bra.uni 	BB2_10;

BB2_9:
	shl.b64 	%rd13, %rd4, 3;
	add.s64 	%rd14, %rd1, %rd13;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f50;
	mov.b16 	%rs9, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f51;
	mov.b16 	%rs10, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f52;
	mov.b16 	%rs11, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f53;
	mov.b16 	%rs12, %temp;
}
	st.global.v4.u16 	[%rd14], {%rs12, %rs11, %rs10, %rs9};

BB2_10:
	ret;
}


