//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64


.visible .entry AdditiveDissolveKernel(
	.param .u64 AdditiveDissolveKernel_param_0,
	.param .u32 AdditiveDissolveKernel_param_1,
	.param .u64 AdditiveDissolveKernel_param_2,
	.param .u32 AdditiveDissolveKernel_param_3,
	.param .u64 AdditiveDissolveKernel_param_4,
	.param .u32 AdditiveDissolveKernel_param_5,
	.param .u32 AdditiveDissolveKernel_param_6,
	.param .u32 AdditiveDissolveKernel_param_7,
	.param .u32 AdditiveDissolveKernel_param_8,
	.param .f32 AdditiveDissolveKernel_param_9
)
{
	.reg .pred 	%p<8>;
	.reg .s16 	%rs<21>;
	.reg .s32 	%r<18>;
	.reg .f32 	%f<80>;
	.reg .s64 	%rd<22>;


	ld.param.u64 	%rd7, [AdditiveDissolveKernel_param_0];
	ld.param.u32 	%r3, [AdditiveDissolveKernel_param_1];
	ld.param.u64 	%rd8, [AdditiveDissolveKernel_param_2];
	ld.param.u32 	%r4, [AdditiveDissolveKernel_param_3];
	ld.param.u64 	%rd9, [AdditiveDissolveKernel_param_4];
	ld.param.u32 	%r5, [AdditiveDissolveKernel_param_5];
	ld.param.u32 	%r6, [AdditiveDissolveKernel_param_6];
	ld.param.u32 	%r7, [AdditiveDissolveKernel_param_7];
	ld.param.u32 	%r8, [AdditiveDissolveKernel_param_8];
	ld.param.f32 	%f44, [AdditiveDissolveKernel_param_9];
	cvta.to.global.u64 	%rd1, %rd9;
	cvta.to.global.u64 	%rd2, %rd8;
	cvta.to.global.u64 	%rd3, %rd7;
	mov.u32 	%r9, %ntid.x;
	mov.u32 	%r10, %ctaid.x;
	mov.u32 	%r11, %tid.x;
	mad.lo.s32 	%r1, %r9, %r10, %r11;
	mov.u32 	%r12, %ntid.y;
	mov.u32 	%r13, %ctaid.y;
	mov.u32 	%r14, %tid.y;
	mad.lo.s32 	%r2, %r12, %r13, %r14;
	setp.lt.s32	%p1, %r1, %r7;
	setp.lt.s32	%p2, %r2, %r8;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_13;
	bra.uni 	BB0_1;

BB0_1:
	mad.lo.s32 	%r15, %r2, %r3, %r1;
	cvt.s64.s32	%rd4, %r15;
	setp.eq.s32	%p4, %r6, 0;
	@%p4 bra 	BB0_3;

	shl.b64 	%rd10, %rd4, 4;
	add.s64 	%rd11, %rd3, %rd10;
	ld.global.v4.f32 	{%f45, %f46, %f47, %f48}, [%rd11];
	mov.f32 	%f71, %f48;
	mov.f32 	%f70, %f47;
	mov.f32 	%f69, %f46;
	mov.f32 	%f68, %f45;
	bra.uni 	BB0_4;

BB0_3:
	shl.b64 	%rd12, %rd4, 3;
	add.s64 	%rd13, %rd3, %rd12;
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd13];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f68, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f69, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f70, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f71, %temp;
	}

BB0_4:
	mad.lo.s32 	%r16, %r2, %r4, %r1;
	cvt.s64.s32	%rd5, %r16;
	@%p4 bra 	BB0_6;

	shl.b64 	%rd14, %rd5, 4;
	add.s64 	%rd15, %rd2, %rd14;
	ld.global.v4.f32 	{%f49, %f50, %f51, %f52}, [%rd15];
	mov.f32 	%f75, %f52;
	mov.f32 	%f74, %f51;
	mov.f32 	%f73, %f50;
	mov.f32 	%f72, %f49;
	bra.uni 	BB0_7;

BB0_6:
	shl.b64 	%rd16, %rd5, 3;
	add.s64 	%rd17, %rd2, %rd16;
	ld.global.v4.u16 	{%rs9, %rs10, %rs11, %rs12}, [%rd17];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs9;
	cvt.f32.f16 	%f72, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs10;
	cvt.f32.f16 	%f73, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs11;
	cvt.f32.f16 	%f74, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs12;
	cvt.f32.f16 	%f75, %temp;
	}

BB0_7:
	mul.ftz.f32 	%f31, %f71, %f75;
	setp.gtu.ftz.f32	%p6, %f44, 0f3F800000;
	@%p6 bra 	BB0_9;

	fma.rn.ftz.f32 	%f53, %f72, %f44, %f68;
	cvt.ftz.sat.f32.f32	%f76, %f53;
	fma.rn.ftz.f32 	%f54, %f73, %f44, %f69;
	cvt.ftz.sat.f32.f32	%f77, %f54;
	fma.rn.ftz.f32 	%f55, %f74, %f44, %f70;
	cvt.ftz.sat.f32.f32	%f78, %f55;
	mov.f32 	%f56, 0f3F800000;
	sub.ftz.f32 	%f57, %f56, %f44;
	mul.ftz.f32 	%f58, %f31, %f44;
	fma.rn.ftz.f32 	%f59, %f71, %f57, %f58;
	cvt.ftz.sat.f32.f32	%f79, %f59;
	bra.uni 	BB0_10;

BB0_9:
	mov.f32 	%f60, 0f40000000;
	sub.ftz.f32 	%f61, %f60, %f44;
	fma.rn.ftz.f32 	%f62, %f68, %f61, %f72;
	cvt.ftz.sat.f32.f32	%f76, %f62;
	fma.rn.ftz.f32 	%f63, %f69, %f61, %f73;
	cvt.ftz.sat.f32.f32	%f77, %f63;
	fma.rn.ftz.f32 	%f64, %f70, %f61, %f74;
	cvt.ftz.sat.f32.f32	%f78, %f64;
	add.ftz.f32 	%f65, %f44, 0fBF800000;
	mul.ftz.f32 	%f66, %f75, %f65;
	fma.rn.ftz.f32 	%f67, %f31, %f61, %f66;
	cvt.ftz.sat.f32.f32	%f79, %f67;

BB0_10:
	mad.lo.s32 	%r17, %r2, %r5, %r1;
	cvt.s64.s32	%rd6, %r17;
	@%p4 bra 	BB0_12;

	shl.b64 	%rd18, %rd6, 4;
	add.s64 	%rd19, %rd1, %rd18;
	st.global.v4.f32 	[%rd19], {%f76, %f77, %f78, %f79};
	bra.uni 	BB0_13;

BB0_12:
	shl.b64 	%rd20, %rd6, 3;
	add.s64 	%rd21, %rd1, %rd20;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f79;
	mov.b16 	%rs17, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f78;
	mov.b16 	%rs18, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f77;
	mov.b16 	%rs19, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f76;
	mov.b16 	%rs20, %temp;
}
	st.global.v4.u16 	[%rd21], {%rs20, %rs19, %rs18, %rs17};

BB0_13:
	ret;
}


