[Filters]
DocumentFilter1            = Projects and Documents (*.DsnWrk;*.PrjPcb;*.PrjFpg;*.PrjCor;*.PrjEmb;*.PrjScr;*.LibPkg;*.pjt;*.DDB;*.schdoc;*.sch;*.OpenBus;*.OpenBusComp;*.pcbdoc;*.pcb;*.cmplib;*.symlib;*.intlib;*.lib;*.schlib;*.pcblib;*.net;*.vhd;*.vhdl;*.v;*.vhdlib;*.verlib;*.vhdtst;*.vertst;*.cpp;*.c;*.hpp;*.h;*.OutJob;*.asm;*.src;*.Constraint;*.DbLib;*.mdl;*.schdot;*.dot;*.edif;*.edf;*.edn;*.edi;*.nsx;*.ckt;*.sdf;*.bas;*.pas;*.inc;*.SwPlatform))
DocumentFilter2            = PCB design file (*.pcbdoc; *.pcb; *.schdoc; *.sch; *.net; *.edif; *.edf; *.edn; *.edi; *.lib; *.schlib; *.pcblib; *.OutJob; *.DbLink; *.DbLib; *.Constraint)
DocumentFilter3            = FPGA design file (*.vhd; *.vhdl; *.v; *.vhdtst; *.vertst; *.schdoc; *.sch; *.OpenBus; *.edif; *.edf; *.edn; *.edi; *.lib; *.schlib; *.vhdlib; *.verlib; *.OutJob; *.DbLink; *.DbLib; *.Constraint)
DocumentFilter4            = Software source file (*.cpp; *.c; *.hpp; *.h; *.asm; *.src; ; *.SwPlatform; *.Constraint )
DocumentFilter5            = Project file (*.PrjPcb; *.PrjFpg; *.PrjCor; *.PrjEmb; *.LibPkg; *.pjt; *.DDB; *.PrjScr)
DocumentFilter6            = Component library (*.CmpLib)
DocumentFilter7            = PCB file (*.pcbdoc; *.pcb)
DocumentFilter8            = PCB library (*.pcblib; *.lib)
DocumentFilter9            = Schematic file (*.schdoc; *.sch; *.OpenBus)
DocumentFilter10           = Symbol library (*.symlib)
DocumentFilter11           = Schematic library (*.schlib; *.lib)
DocumentFilter12           = Schematic template (*.schdot; *.dot)
DocumentFilter13           = Integrated Library (*.intlib)
DocumentFilter14           = Report file (*.rep; *.log; *.rpt; *.drc; *.erc; *.bom)
DocumentFilter15           = VHDL file (*.vhd; *.vhdl; *.vhdtst; *.vhdlib; *.verlib)
DocumentFilter16           = Verilog file (*.v; *.vertst)
DocumentFilter17           = Netlist file (*.net; *.vhd; *.v; *.edif; *.edf; *.edn; *.edi)
DocumentFilter18           = Mixed-signal sim file (*.mdl; *.nsx; *.ckt; *.sdf; *.lb)
DocumentFilter19           = FPGA Design file (*.vhd; *.vhdl; *.v; *.vhdlib; *.verlib; *.vhdtst; *.vertst; *.so; *.wo)
DocumentFilter20           = Script file (*.bas; *.pas; *.inc; *.tcl; *.vbs; *.js)
DocumentFilter21           = C Source file (*.c)
DocumentFilter22           = C++ Source file (*.cpp)
DocumentFilter23           = Header file (*.hpp; *.h)
DocumentFilter24           = Assembler file (*.asm; *.src)
DocumentFilter25           = Constraint Files (*.Constraint)
DocumentFilter26           = CAM file (*.cam; *.g??; *.drr; *.pik; *.bom)
DocumentFilter27           = Design Workspace file (*.DsnWrk; *.PrjGrp)
DocumentFilter28           = Text file (*.txt)
DocumentFilter29           = OrCAD Layout file (*.max)
DocumentFilter30           = OrCAD Max Library file (*.llb)
DocumentFilter31           = P-CAD V15, V16 or V17 file (*.pcb)
DocumentFilter32           = PADS PCB file (*.asc)
DocumentFilter33           = Specctra Design file (*.dsn)
DocumentFilter34           = Protel 99SE Design Databases (*.DDB)
DocumentFilter35           = OrCAD Capture Design (*.DSN)
DocumentFilter36           = OrCAD Capture Library (*.OLB)
DocumentFilter37           = OrCAD CIS Configuration file (*.DBC)
DocumentFilter38           = P-CAD V16, V17 Schematic (*.SCH)
DocumentFilter39           = P-CAD V16, V17 Schematic Library (*.LIA; *.LIB)
DocumentFilter40           = CircuitMaker 2000 Design (*.CKT)
DocumentFilter41           = CircuitMaker 2000 Binary USER Library (*.LIB)
DocumentFilter42           = Output Job Files (*.OutJob)
DocumentFilter43           = Database Link Files (*.DbLink)
DocumentFilter44           = Database Lib Files (*.DBLib)
DocumentFilter45           = PCB3D Library Files (*.PCB3DLib)
DocumentFilter46           = PCB3D Files (*.PCB3D)
DocumentFilter47           = Page Files (*.page)
DocumentFilter48           = Constraint Files (*.Constraint)
DocumentFilter49           = OpenBus Components (*.OpenBusComp)
DocumentFilter50           = Software Platform Configuration Files (*.SwPlatform)
DocumentFilter51           = All files (*.*)

ProjectFilter1             = Project file (*.PrjPcb; *.PrjFpg; *.PrjCor; *.PrjEmb; *.LibPkg; *.pjt; *.DDB; *.PrjScr)
ProjectFilter2             = PCB Project file (*.PrjPcb)
ProjectFilter3             = FPGA Project file (*.PrjFpg)
ProjectFilter4             = Core Project file (*.PrjCor)
ProjectFilter5             = Embedded Project file (*.PrjEmb)
ProjectFilter6             = Tasking Project file (*.pjt)
ProjectFilter7             = Script Project file (*.PrjScr)
ProjectFilter8             = Integrated Library Package (*.LibPkg)
ProjectFilter9             = Protel 99SE Design Databases (*.DDB)
ProjectFilter10            = OrCAD Capture Design (*.DSN)
ProjectFilter11            = OrCAD Capture Library (*.OLB)
ProjectFilter12            = P-CAD V16 ASCII Schematic (*.SCH)
ProjectFilter13            = P-CAD V16 ASCII Library (*.LIA)
ProjectFilter14            = SIMetrix ASCII Schematic (*.SXSCH)
ProjectFilter15            = SIMetrix ASCII Library (*.SXSLB)

WorkspaceFilter1           = Workspace file (*.DsnWrk; *.PrjGrp)
WorkspaceFilter2           = Project Group file (*.PrjGrp)
WorkspaceFilter3           = Design Workspace file (*.DsnWrk)

ProjectSourceFilter_PCB1   = Design file (*.pcbdoc; *.pcb; *.schdoc; *.sch; *.net; *.edif; *.edf; *.edn; *.edi; *.cmplib; *.symlib; *.lib; *.schlib; *.pcblib; *.OutJob; *.DbLink; *.DbLib; *.Constraint)
ProjectSourceFilter_PCB2   = Schematic file (*.sch; *.schdoc)
ProjectSourceFilter_PCB3   = PCB file (*.pcb; *.pcbdoc)
ProjectSourceFilter_PCB4   = Library file (*.intlib; *.lib; *.schlib; *.pcblib)
ProjectSourceFilter_PCB5   = Netlist file (*.net; *.edif; *.edf; *.edn; *.edi)
ProjectSourceFilter_PCB6   = Mixed-signal sim file (*.mdl; *.nsx; *.ckt; *.lb)
ProjectSourceFilter_PCB7   = Output Job Files (*.OutJob)
ProjectSourceFilter_PCB8   = Database Link Files (*.DbLink)
ProjectSourceFilter_PCB9   = Database Library Files (*.DbLib)
ProjectSourceFilter_PCB10  = Constraint Files (*.Constraint)
ProjectSourceFilter_PCB11  = All files (*.*)

ProjectSourceFilter_FPGA1  = Design file (*.vhd; *.vhdl; *.v; *.vhdtst; *.vertst; *.schdoc; *.sch; *.OpenBus; *.edif; *.edf; *.edn; *.edi; *.lib; *.schlib; *.vhdlib; *.verlib; *.OutJob; *.DbLink; *.DbLib; *.Constraint; *.c; *.h)
ProjectSourceFilter_FPGA2  = Schematic file (*.sch; *.schdoc; *.OpenBus)
ProjectSourceFilter_FPGA3  = VHDL file (*.vhd; *.vhdl; *.vhdtst)
ProjectSourceFilter_FPGA4  = Verilog file (*.v; *.vertst)
ProjectSourceFilter_FPGA5  = VHDL Library file (*.vhdlib)
ProjectSourceFilter_FPGA6  = Verilog Library file (*.verlib)
ProjectSourceFilter_FPGA7  = Netlist file (*.edif; *.edf; *.edn; *.edi)
ProjectSourceFilter_FPGA8  = Library file (*.intlib; *.lib; *.schlib)
ProjectSourceFilter_FPGA9  = Output Job Files (*.OutJob)
ProjectSourceFilter_FPGA10 = FPGA Target (*.FpgTrg)
ProjectSourceFilter_FPGA11 = Database Link Files (*.DbLink)
ProjectSourceFilter_FPGA12 = Database Library Files (*.DbLib)
ProjectSourceFilter_FPGA13 = Constraint Files (*.Constraint)
ProjectSourceFilter_FPGA14 = C Source Files (*.c; *.h)
ProjectSourceFilter_FPGA15 = All files (*.*)

ProjectSourceFilter_CORE1  = Design file (*.vhd; *.vhdl; *.v; *.vhdtst; *.vertst; *.schdoc; *.sch; *.edif; *.edf; *.edn; *.edi; *.lib; *.schlib; *.vhdlib; *.verlib; *.OutJob; *.DbLinl; *.Constraint; *.c; *.h)
ProjectSourceFilter_CORE2  = Schematic file (*.sch; *.schdoc)
ProjectSourceFilter_CORE3  = VHDL file (*.vhd; *.vhdl; *.vhdtst)
ProjectSourceFilter_CORE4  = Verilog file (*.v; *.vertst)
ProjectSourceFilter_CORE5  = VHDL Library file (*.vhdlib)
ProjectSourceFilter_CORE6  = Verilog Library file (*.verlib)
ProjectSourceFilter_CORE7  = Netlist file (*.edif; *.edf; *.edn; *.edi)
ProjectSourceFilter_CORE8  = Library file (*.intlib; *.lib; *.schlib)
ProjectSourceFilter_CORE9  = Output Job Files (*.OutJob)
ProjectSourceFilter_CORE10 = Database Link Files (*.DbLink)
ProjectSourceFilter_CORE11 = Database Library Files (*.DbLib)
ProjectSourceFilter_CORE12 = Constraint Files (*.Constraint)
ProjectSourceFilter_CORE13 = C Source Files (*.c; *.h)
ProjectSourceFilter_CORE14 = All files (*.*)

ProjectSourceFilter_EMB1   = Software source file (*.cpp; *.c; *.hpp; *.h; *.asm; *.src; *.oil; *.Constraint;*.SwPlatform)
ProjectSourceFilter_EMB2   = C Source file (*.c)
ProjectSourceFilter_EMB3   = C++ Source file (*.cpp)
ProjectSourceFilter_EMB4   = Header file (*.hpp; *.h)
ProjectSourceFilter_EMB5   = Assembler file (*.asm; *.src)
ProjectSourceFilter_EMB6   = Constraint Files (*.Constraint)
ProjectSourceFilter_EMB7   = OIL source file (*.oil)
ProjectSourceFilter_EMB8   = Software Platform Configuration file (*.SwPlatform)
ProjectSourceFilter_EMB9   = All files (*.*)

ProjectSourceFilter_ILB1   = Component library (*.cmplib)
ProjectSourceFilter_ILB2   = Symbol library (*.symlib)
ProjectSourceFilter_ILB3   = PCB library (*.pcblib; *.lib)
ProjectSourceFilter_ILB4   = Schematic library (*.schlib; *.lib)
ProjectSourceFilter_ILB5   = PCB3D library (*.PCB3DLib; *.lib)
ProjectSourceFilter_ILB6   = Mixed-signal sim model file (*.mdl; *.ckt; *.lb)
ProjectSourceFilter_ILB7   = All files (*.*)

ECOFileFilter1             = ECO and WAS-IS file (*.was; *.eco)
ECOFileFilter2             = ECO file (*.eco)
ECOFileFilter3             = WAS-IS file (*.was)

ProjectSourceFilter_SCR1   = Script Files (*.pas; *.inc; *.vbs; *.js; *.tcl; *.bas)
ProjectSourceFilter_SCR2   = Pascal Script Files (*.pas; *.inc)
ProjectSourceFilter_SCR3   = VBScript Files (*.vbs)
ProjectSourceFilter_SCR4   = JavaScript Files (*.js)
ProjectSourceFilter_SCR5   = Tcl/Tk Script Files (*.tcl)
ProjectSourceFilter_SCR6   = Enable Basic Files (*.bas)
ProjectSourceFilter_SCR7   = All files (*.*)
