# XST messages to ignore

WARNING:Xst:37 - Unknown property "FPGA_IOSTANDARD"
WARNING:Xst:37 - Unknown property "FPGA_PINNUM"
WARNING:Xst:37 - Unknown property "FPGA_CLOCK_PIN"
WARNING:Xst:37 - Unknown property "FPGA_CLOCK"
WARNING:Xst:37 - Unknown property "FPGA_DRIVE"
Possible simulation mismatch.
ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN

# Altera messages to ignore

Warning: Detecting "Precision Synthesis" as EDA design entry or synthesis tool that generated EDIF Input file
Warning: Feature SignalTap II is not available with your current license
Warning: Feature Device Migration is not available with your current license
Warning: Ignored DEFAULT_DEVICE_OPTIONS section -- assignment ON_CHIP_BITSTREAM_DECOMPRESSION will be made in the CHIP section

# Actel messages to ignore

Warning:  NOM3812:   Overwritting the contents of the redeclared cell

# Lattice messages to ignore

WARNING - edif2ngd: Unsupported property
WARNING - ngdbuild: logical net
WARNING - map: logical net
errors. Press ^C to abort, or routing will continue.
errors.  For more information, see online help subjects "Place &