Address
Address1
Address2
Address3
Address4
Address5
Address6
Address7
Address8
Address9
Address10
ApprovedBy
ArchiveName
Author
CheckedBy
ChildCore1
ChildCore2
ChildCore3
ChildCore4
ChildCore5
ChildModel
ChildModel1
ChildModel2
ChildModel3
ChildModel4
ChildModel5
ChildModel6
ChildModel7
ChildModel8
ChildModel9
ChildModel10
ChildModel11
ChildModel12
ChildModel13
ChildModel14
ChildModel15
ChildModel16
ChildModel17
ChildModel18
ChildModel19
Class
Class I
Class II
Class III
Class IV
Class V
Class VI
Clk_Count
Clk_Freq_Mhz
Clk_LowFreq_Mode
ClkA_Operation
ClkB_Operation
ClkC_Operation
ClkD_Operation
ClockTrigger
Comment
Comment_1
CompanyName
Component Kind
ComponentLink1Description
ComponentLink1URL
ComponentLink2Description
ComponentLink2URL
ComponentLink3Description
ComponentLink3URL
ComponentLink4Description
ComponentLink4URL
ConfiguratorName
ConfigurationParameters
ConfigurationName
CurrentConfigurationName
ConstantExpression
Control
CoreModel1
CoreModel2
CoreModel3
CoreModel4
CoreModel5
Core Revision
CrossRef
CurrentDate
CurrentTime
Date
DataSheet
Description
Design_ Item_ID
Direction
DisplayUpdate
DivisorRate
Divisor_Rate
DocumentFullPathAndName
DocumentName
DocumentNumber
DrawnBy
DutyCycle
Duty_Cycle
Enable
Engineer
Footprint
FPGAVendor
FPGA Vendor
FPGA_CLOCK_FREQUENCY
FPGA_CLOCK_DUTY_CYCLE
FPGA_PINNUM
FPGA_RESERVE_PIN
Functional_Class
FunctionalClass
Functional Class
HelpURL
ImagePath
IncludeInDSF
JTAG_Index
LastRevisionNo
LatestRevisionDate
LatestRevisionNote
Library Name
Library Reference
Loadable
Manufacturer
Memgen
Memory_Contentfile
Memory_Depth
Memory_DepthA
Memory_DepthB
Memory_Type
Memory_Width
Memory_WidthA
Memory_WidthB
Memory_ClockEdge
Memory_EnablePin
Memory_EnablePinA
Memory_EnablePinB
Memory_Configuration
Memory_ByteWrites
ModifiedDate
Nexus_Core
NEXUS_JTAG_CONNECTOR
Nexus_JTag_Device
Nexus_JTag_Index
Nexus_JTag_Order
Note
Organisation
Organization
PageSetup
PCAD Pattern
PCAD_Pattern
PCB3D
PinNumberDisplay
Port_Size
Port Size
PortSize
PortStyle
Port_Style
PortType
ProgramLogicalTopAddress
ProjectName
Protel Footprint
Protel_Footprint
Published
Publisher
ReferenceDesignId
Reset
Revision
Rule
SheetNumber
SheetTotal
Signal Integrity
Signal_Integrity
Simulation
SourceFile
Source_File
SubClass
Sub_Class
SuppressERC
SymbolGenerator_Hidden
SynbolGenerator_Clock
Symbol_ Reference
Text_Field1
Text_Field2
Text_Field3
Text_Field4
Text_Field5
Text_Field6
Text_Field7
Text_Field8
Text_Field9
Text_Field10
Text_Field11
Text_Field12
Text_Field13
Text_Field14
Text_Field15
Text_Field16
Time
Title
UseInDSF
VHDLEntity
VHDLIB_SIM
VHDLIB_SYN
XILINX EQUIVALENT
XilinxEquivalent
X_PortSize
X_Port_Size
ZippedEdifBaseName
ZippedChildEdifName1
ZippedChildEdifName2
ZippedChildEdifName3
ZippedChildEdifName4
ZippedChildEdifName5