# Load Quartus II Tcl Project package
# For Altera Quartus II 3.0

package require ::quartus::project

set need_to_close_project 1
set make_assignments 1
set enable_pld_flow .ReplaceEnablePLDFlow

# Check that the right project is open
if {[is_project_open]} {
	if {[string compare $quartus(project) ".ReplaceProjectName"]} {
		puts "Project .ReplaceProjectName is not open"
		set make_assignments 0
	}
} else {
	# Only open if not already open
	if {[project_exists .ReplaceProjectName]} {
		project_open -cmp .ReplaceProjectName .ReplaceProjectName
	} else {
		project_new .ReplaceProjectName
	}
	set need_to_close_project 1
}

file delete -force .ReplaceProjectName.quartus
file delete -force .ReplaceProjectName.psf
file delete -force .ReplaceProjectName.esf
file delete -force .ReplaceProjectName.csf
file delete -force .ReplaceProjectName.ssf
file delete -force .ReplaceProjectName.fsf
file delete -force db

# Make assignments
if {$make_assignments} {
	# Project Assignments
        
        # Add the top level design file 
	set_global_assignment -name "COMPILER_SETTINGS" ".ReplaceProjectName"

        if [file exists .ReplaceProjectName.edn] {
            set_global_assignment -name "EDIF_FILE" ".ReplaceProjectName.edn"
        } else {
            if [file exists .ReplaceProjectName.vqm] {
                set_global_assignment -name "VQM_FILE" ".ReplaceProjectName.vqm"
            }
        }

        # Add a listing of all the HDL source files
        if [file exists .ReplaceProjectName_SourceHDLFiles.tcl] {
           source [file join ".ReplaceProjectName_SourceHDLFiles.tcl"];
        }

        # Add a listing of all the macro files
        if [file exists .ReplaceProjectName_MacroFiles.tcl] {
          source [file join ".ReplaceProjectName_MacroFiles.tcl"];
        }

	set_global_assignment -name "SIMULATOR_SETTINGS" ".ReplaceProjectName"
	set_global_assignment -name "SOFTWARE_SETTINGS" "Debug"
	set_global_assignment -name "SOFTWARE_SETTINGS" "Release"

	set_global_assignment -name "ACLK_CAT" "OFF"
	set_global_assignment -name "ACLK_RULE_IMSZER_ADOMAIN" "OFF"
	set_global_assignment -name "ACLK_RULE_NO_SZER_ACLK_DOMAIN" "OFF"
	set_global_assignment -name "ACLK_RULE_SZER_BTW_ACLK_DOMAIN" "OFF"
	set_global_assignment -name "ASSG_CAT" "OFF"
	set_global_assignment -name "ASSG_RULE_MISSING_FMAX" "OFF"
	set_global_assignment -name "ASSG_RULE_MISSING_TIMING" "OFF"
	set_global_assignment -name "CLK_CAT" "OFF"
	set_global_assignment -name "CLK_RULE_ALL" "OFF"
	set_global_assignment -name "CLK_RULE_CLKNET_CLKSPINES" "OFF"
	set_global_assignment -name "CLK_RULE_COMB_CLOCK" "OFF"
	set_global_assignment -name "CLK_RULE_GATING_SCHEME" "OFF"
	set_global_assignment -name "CLK_RULE_INPINS_CLKNET" "OFF"
	set_global_assignment -name "CLK_RULE_INV_CLOCK" "OFF"
	set_global_assignment -name "CLK_RULE_MIX_EDGES" "OFF"
	set_global_assignment -name "HCPY_ALOAD_SIGNALS" "OFF"
	set_global_assignment -name "NONSYNCHSTRUCT_RULE_ASYN_RAM" "OFF"
	set_global_assignment -name "HCPY_CAT" "OFF"
	set_global_assignment -name "HCPY_EXCEED_RAM_USAGE" "OFF"
	set_global_assignment -name "HCPY_EXCEED_USER_IO_USAGE" "OFF"
	set_global_assignment -name "HCPY_ILLEGAL_HC_DEV_PKG" "OFF"
	set_global_assignment -name "HCPY_VREF_PINS" "OFF"
	set_global_assignment -name "NONSYNCHSTRUCT_CAT" "OFF"
	set_global_assignment -name "NONSYNCHSTRUCT_RULE_COMBLOOP" "OFF"
	set_global_assignment -name "NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE" "OFF"
	set_global_assignment -name "NONSYNCHSTRUCT_RULE_DELAY_CHAIN" "OFF"
	set_global_assignment -name "NONSYNCHSTRUCT_RULE_DLATCH" "OFF"
	set_global_assignment -name "NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN" "OFF"
	set_global_assignment -name "NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED" "OFF"
	set_global_assignment -name "NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR" "OFF"
	set_global_assignment -name "NONSYNCHSTRUCT_RULE_REG_LOOP" "OFF"
	set_global_assignment -name "NONSYNCHSTRUCT_RULE_RIPPLE_CLK" "OFF"
	set_global_assignment -name "NONSYNCHSTRUCT_RULE_SRLATCH" "OFF"
	set_global_assignment -name "RESET_CAT" "OFF"
	set_global_assignment -name "RESET_RULE_ALL" "OFF"
	set_global_assignment -name "RESET_RULE_COMB_ASYNCH_RESET" "OFF"
	set_global_assignment -name "RESET_RULE_IMSYNCH_ASYNCH_DOMAIN" "OFF"
	set_global_assignment -name "RESET_RULE_IMSYNCH_EXRESET" "OFF"
	set_global_assignment -name "RESET_RULE_INPINS_RESETNET" "OFF"
	set_global_assignment -name "RESET_RULE_REG_ASNYCH" "OFF"
	set_global_assignment -name "RESET_RULE_UNSYNCH_ASYNCH_DOMAIN" "OFF"
	set_global_assignment -name "RESET_RULE_UNSYNCH_EXRESET" "OFF"
	set_global_assignment -name "SIGNALRACE_CAT" "OFF"
	set_global_assignment -name "SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN" "OFF"
	set_global_assignment -name "SIGNALRACE_RULE_TRISTATE" "OFF"
	set_global_assignment -name "TIMING_CAT" "OFF"
	set_global_assignment -name "TIMING_RULE_COIN_CLKEDGE" "OFF"
	set_global_assignment -name "TIMING_RULE_HIGH_FANOUTS" "OFF"
	set_global_assignment -name "TIMING_RULE_SHIFT_REG" "OFF"
	set_global_assignment -name "LIMIT_AHDL_INTEGERS_TO_32_BITS" "OFF"
	set_global_assignment -name "USE_LPM_FOR_AHDL_OPERATORS" "ON"
	set_global_assignment -name "ALLOW_POWER_UP_DONT_CARE" "ON"
	set_global_assignment -name "AUTO_CARRY_CHAINS" "ON"
	set_global_assignment -name "AUTO_CASCADE_CHAINS" "ON"
	set_global_assignment -name "AUTO_DELAY_CHAINS" "ON"
	set_global_assignment -name "AUTO_DSP_RECOGNITION" "ON"
	set_global_assignment -name "AUTO_GLOBAL_CLOCK" "ON"
	set_global_assignment -name "AUTO_GLOBAL_MEMORY_CONTROLS" "OFF"
	set_global_assignment -name "AUTO_GLOBAL_OE" "ON"
	set_global_assignment -name "AUTO_GLOBAL_REGISTER_CONTROLS" "ON"
	set_global_assignment -name "AUTO_FAST_INPUT_REGISTERS" "OFF"
	set_global_assignment -name "AUTO_LCELL_INSERTION" "ON"
	set_global_assignment -name "AUTO_MERGE_PLLS" "ON"
	set_global_assignment -name "AUTO_OPEN_DRAIN_PINS" "ON"
	set_global_assignment -name "AUTO_FAST_OUTPUT_ENABLE_REGISTERS" "OFF"
	set_global_assignment -name "AUTO_FAST_OUTPUT_REGISTERS" "OFF"
	set_global_assignment -name "AUTO_PARALLEL_EXPANDERS" "ON"
	set_global_assignment -name "AUTO_RAM_RECOGNITION" "ON"
	set_global_assignment -name "AUTO_IMPLEMENT_IN_ROM" "OFF"
	set_global_assignment -name "AUTO_SHIFT_REGISTER_RECOGNITION" "ON"
	set_global_assignment -name "AUTO_TURBO_BIT" "ON"
	set_global_assignment -name "CARRY_CHAIN_LENGTH" "48"
	set_global_assignment -name "STRATIX_CARRY_CHAIN_LENGTH" "70"
	set_global_assignment -name "CARRY_OUT_PINS_LCELL_INSERT" "ON"
	set_global_assignment -name "CASCADE_CHAIN_LENGTH" "2"
	set_global_assignment -name "DSP_BLOCK_BALANCING" "AUTO"
	set_global_assignment -name "REMOVE_DUPLICATE_LOGIC" "OFF"
	set_global_assignment -name "REMOVE_DUPLICATE_REGISTERS" "OFF"
	set_global_assignment -name "ENABLE_BUS_HOLD_CIRCUITRY" "OFF"
	set_global_assignment -name "IGNORE_CARRY_BUFFERS" "OFF"
	set_global_assignment -name "IGNORE_CASCADE_BUFFERS" "OFF"
	set_global_assignment -name "IGNORE_GLOBAL_BUFFERS" "OFF"
	set_global_assignment -name "IGNORE_LCELL_BUFFERS" "OFF"
	set_global_assignment -name "MAX7000_IGNORE_LCELL_BUFFERS" "AUTO"
	set_global_assignment -name "IGNORE_ROW_GLOBAL_BUFFERS" "OFF"
	set_global_assignment -name "IGNORE_SOFT_BUFFERS" "OFF"
	set_global_assignment -name "MAX7000_IGNORE_SOFT_BUFFERS" "OFF"
	set_global_assignment -name "NORMAL_LCELL_INSERT" "ON"
	set_global_assignment -name "NOT_GATE_PUSH_BACK" "ON"
	set_global_assignment -name "CYCLONE_OPTIMIZATION_TECHNIQUE" "AREA"
	set_global_assignment -name "MAX7000_OPTIMIZATION_TECHNIQUE" "SPEED"
	set_global_assignment -name "STRATIX_OPTIMIZATION_TECHNIQUE" "SPEED"
	set_global_assignment -name "PCI_IO" "OFF"
	set_global_assignment -name "PARALLEL_EXPANDER_CHAIN_LENGTH" "16"
	set_global_assignment -name "MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH" "4"
	set_global_assignment -name "AUTO_PACKED_REGISTERS" "OFF"
	set_global_assignment -name "AUTO_PACKED_REG_CYCLONE" "NORMAL"
	set_global_assignment -name "AUTO_PACKED_REGISTERS_STRATIX" "NORMAL"
	set_global_assignment -name "REMOVE_REDUNDANT_LOGIC_CELLS" "OFF"
	set_global_assignment -name "SLOW_SLEW_RATE" "OFF"
	set_global_assignment -name "STATE_MACHINE_PROCESSING" "AUTO"
	set_global_assignment -name "MAX7000_TECHNOLOGY_MAPPER" "PRODUCT TERM"
	set_global_assignment -name "STRATIX_TECHNOLOGY_MAPPER" "LUT"
	set_global_assignment -name "TURBO_BIT" "ON"
	set_global_assignment -name "WEAK_PULL_UP_RESISTOR" "OFF"
	set_global_assignment -name "ALLOW_XOR_GATE_USAGE" "ON"
	set_global_assignment -name "CUT_OFF_CLEAR_AND_PRESET_PATHS" "ON"
	set_global_assignment -name "CUT_OFF_IO_PIN_FEEDBACK" "ON"
	set_global_assignment -name "CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS" "ON"
	set_global_assignment -name "CUT_OFF_READ_DURING_WRITE_PATHS" "ON"
	set_global_assignment -name "DO_MIN_ANALYSIS" "ON"
	set_global_assignment -name "DO_MIN_TIMING" "OFF"
	set_global_assignment -name "INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS" "OFF"
	set_global_assignment -name "DEFAULT_HOLD_MULTICYCLE" "SAME AS MULTICYCLE"
	set_global_assignment -name "IGNORE_CLOCK_SETTINGS" ".ReplaceIgnoreClockSettings"
	set_global_assignment -name "MAX_SCC_SIZE" "50"
	set_global_assignment -name "NUMBER_OF_DESTINATION_TO_REPORT" "10"
	set_global_assignment -name "NUMBER_OF_PATHS_TO_REPORT" "200"
	set_global_assignment -name "RUN_ALL_TIMING_ANALYSES" "OFF"
	set_global_assignment -name "NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT" "10"
	set_global_assignment -name "ENABLE_IP_DEBUG" "OFF"
	set_global_assignment -name "VERILOG_INPUT_VERSION" "VERILOG_2001"
	set_global_assignment -name "VHDL_INPUT_VERSION" "VHDL93"
	set_global_assignment -name "VHDL_SHOW_LMF_MAPPING_MESSAGES" "ON"
	set_global_assignment -name "LAST_QUARTUS_VERSION" -section_id ".ReplaceProjectName" "3.0 SP2"
	set_global_assignment -name "ORIGINAL_QUARTUS_VERSION" -section_id ".ReplaceProjectName" "3.0 SP2"
	set_global_assignment -name "PROJECT_CREATION_TIME_DATE" -section_id ".ReplaceProjectName" "19:10:27  DECEMBER 22, 2003"
	set_global_assignment -name "SHOW_REGISTRATION_MESSAGE" -section_id ".ReplaceProjectName" "ON"
	set_global_assignment -name "EDA_BOARD_DESIGN_TOOL" -section_id ".ReplaceProjectName" "<None>"
	set_global_assignment -name "EDA_DESIGN_ENTRY_SYNTHESIS_TOOL" -section_id ".ReplaceProjectName" "<None>"
	set_global_assignment -name "EDA_FORMAL_VERIFICATION_TOOL" -section_id ".ReplaceProjectName" "<None>"
	set_global_assignment -name "EDA_RESYNTHESIS_TOOL" -section_id ".ReplaceProjectName" "<None>"
	set_global_assignment -name "EDA_SIMULATION_TOOL" -section_id ".ReplaceProjectName" "<None>"
	set_global_assignment -name "EDA_TIMING_ANALYSIS_TOOL" -section_id ".ReplaceProjectName" "<None>"
	set_global_assignment -name "EDA_INPUT_DATA_FORMAT" -section_id "eda_design_synthesis" "EDIF"
	set_global_assignment -name "EDA_INPUT_GND_NAME" -section_id "eda_design_synthesis" "GND"
	set_global_assignment -name "EDA_INPUT_VCC_NAME" -section_id "eda_design_synthesis" "VCC"
	set_global_assignment -name "EDA_RUN_TOOL_AUTOMATICALLY" -section_id "eda_design_synthesis" "OFF"
	set_global_assignment -name "EDA_OUTPUT_DATA_FORMAT" -section_id "eda_design_synthesis" "NONE"
	set_global_assignment -name "EDA_SHOW_LMF_MAPPING_MESSAGES" -section_id "eda_design_synthesis" "ON"
	set_global_assignment -name "RESYNTHESIS_OPTIMIZATION_EFFORT" -section_id "eda_design_synthesis" "NORMAL"
	set_global_assignment -name "RESYNTHESIS_PHYSICAL_SYNTHESIS" -section_id "eda_design_synthesis" "NORMAL"
	set_global_assignment -name "RESYNTHESIS_RETIMING" -section_id "eda_design_synthesis" "FULL"
	set_global_assignment -name "USE_GENERATED_PHYSICAL_CONSTRAINTS" -section_id "eda_design_synthesis" "ON"
	set_global_assignment -name "EDA_FLATTEN_BUSES" -section_id "eda_simulation" "OFF"
	set_global_assignment -name "EDA_GENERATE_FUNCTIONAL_NETLIST" -section_id "eda_simulation" "OFF"
	set_global_assignment -name "EDA_RUN_TOOL_AUTOMATICALLY" -section_id "eda_simulation" "OFF"
	set_global_assignment -name "EDA_MAINTAIN_DESIGN_HIERARCHY" -section_id "eda_simulation" "OFF"
	set_global_assignment -name "EDA_MAP_ILLEGAL_CHARACTERS" -section_id "eda_simulation" "OFF"
	set_global_assignment -name "EDA_OUTPUT_DATA_FORMAT" -section_id "eda_simulation" "NONE"
	set_global_assignment -name "EDA_TRUNCATE_LONG_HIERARCHY_PATHS" -section_id "eda_simulation" "OFF"
	set_global_assignment -name "EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION" -section_id "eda_simulation" "OFF"
	set_global_assignment -name "EDA_WRITE_DEVICE_CONTROL_PORTS" -section_id "eda_simulation" "OFF"
	set_global_assignment -name "RESYNTHESIS_OPTIMIZATION_EFFORT" -section_id "eda_simulation" "NORMAL"
	set_global_assignment -name "RESYNTHESIS_PHYSICAL_SYNTHESIS" -section_id "eda_simulation" "NORMAL"
	set_global_assignment -name "RESYNTHESIS_RETIMING" -section_id "eda_simulation" "FULL"
	set_global_assignment -name "USE_GENERATED_PHYSICAL_CONSTRAINTS" -section_id "eda_simulation" "ON"
	set_global_assignment -name "EDA_FLATTEN_BUSES" -section_id "eda_timing_analysis" "OFF"
	set_global_assignment -name "EDA_GENERATE_FUNCTIONAL_NETLIST" -section_id "eda_timing_analysis" "OFF"
	set_global_assignment -name "EDA_LAUNCH_CMD_LINE_TOOL" -section_id "eda_timing_analysis" "OFF"
	set_global_assignment -name "EDA_RUN_TOOL_AUTOMATICALLY" -section_id "eda_timing_analysis" "OFF"
	set_global_assignment -name "EDA_MAINTAIN_DESIGN_HIERARCHY" -section_id "eda_timing_analysis" "OFF"
	set_global_assignment -name "EDA_MAP_ILLEGAL_CHARACTERS" -section_id "eda_timing_analysis" "OFF"
	set_global_assignment -name "EDA_OUTPUT_DATA_FORMAT" -section_id "eda_timing_analysis" "NONE"
	set_global_assignment -name "EDA_TRUNCATE_LONG_HIERARCHY_PATHS" -section_id "eda_timing_analysis" "OFF"
	set_global_assignment -name "EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION" -section_id "eda_timing_analysis" "OFF"
	set_global_assignment -name "EDA_WRITE_DEVICE_CONTROL_PORTS" -section_id "eda_timing_analysis" "OFF"
	set_global_assignment -name "RESYNTHESIS_OPTIMIZATION_EFFORT" -section_id "eda_timing_analysis" "NORMAL"
	set_global_assignment -name "RESYNTHESIS_PHYSICAL_SYNTHESIS" -section_id "eda_timing_analysis" "NORMAL"
	set_global_assignment -name "RESYNTHESIS_RETIMING" -section_id "eda_timing_analysis" "FULL"
	set_global_assignment -name "USE_GENERATED_PHYSICAL_CONSTRAINTS" -section_id "eda_timing_analysis" "ON"
	set_global_assignment -name "EDA_FLATTEN_BUSES" -section_id "eda_board_design" "OFF"
	set_global_assignment -name "EDA_GENERATE_FUNCTIONAL_NETLIST" -section_id "eda_board_design" "OFF"
	set_global_assignment -name "EDA_RUN_TOOL_AUTOMATICALLY" -section_id "eda_board_design" "OFF"
	set_global_assignment -name "EDA_MAINTAIN_DESIGN_HIERARCHY" -section_id "eda_board_design" "OFF"
	set_global_assignment -name "EDA_MAP_ILLEGAL_CHARACTERS" -section_id "eda_board_design" "OFF"
	set_global_assignment -name "EDA_OUTPUT_DATA_FORMAT" -section_id "eda_board_design" "NONE"
	set_global_assignment -name "EDA_TRUNCATE_LONG_HIERARCHY_PATHS" -section_id "eda_board_design" "OFF"
	set_global_assignment -name "EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION" -section_id "eda_board_design" "OFF"
	set_global_assignment -name "EDA_WRITE_DEVICE_CONTROL_PORTS" -section_id "eda_board_design" "OFF"
	set_global_assignment -name "RESYNTHESIS_OPTIMIZATION_EFFORT" -section_id "eda_board_design" "NORMAL"
	set_global_assignment -name "RESYNTHESIS_PHYSICAL_SYNTHESIS" -section_id "eda_board_design" "NORMAL"
	set_global_assignment -name "RESYNTHESIS_RETIMING" -section_id "eda_board_design" "FULL"
	set_global_assignment -name "USE_GENERATED_PHYSICAL_CONSTRAINTS" -section_id "eda_board_design" "ON"
	set_global_assignment -name "EDA_FLATTEN_BUSES" -section_id "eda_formal_verification" "OFF"
	set_global_assignment -name "EDA_GENERATE_FUNCTIONAL_NETLIST" -section_id "eda_formal_verification" "OFF"
	set_global_assignment -name "EDA_RUN_TOOL_AUTOMATICALLY" -section_id "eda_formal_verification" "OFF"
	set_global_assignment -name "EDA_MAINTAIN_DESIGN_HIERARCHY" -section_id "eda_formal_verification" "OFF"
	set_global_assignment -name "EDA_MAP_ILLEGAL_CHARACTERS" -section_id "eda_formal_verification" "OFF"
	set_global_assignment -name "EDA_OUTPUT_DATA_FORMAT" -section_id "eda_formal_verification" "NONE"
	set_global_assignment -name "EDA_TRUNCATE_LONG_HIERARCHY_PATHS" -section_id "eda_formal_verification" "OFF"
	set_global_assignment -name "EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION" -section_id "eda_formal_verification" "OFF"
	set_global_assignment -name "EDA_WRITE_DEVICE_CONTROL_PORTS" -section_id "eda_formal_verification" "OFF"
	set_global_assignment -name "RESYNTHESIS_OPTIMIZATION_EFFORT" -section_id "eda_formal_verification" "NORMAL"
	set_global_assignment -name "RESYNTHESIS_PHYSICAL_SYNTHESIS" -section_id "eda_formal_verification" "NORMAL"
	set_global_assignment -name "RESYNTHESIS_RETIMING" -section_id "eda_formal_verification" "FULL"
	set_global_assignment -name "USE_GENERATED_PHYSICAL_CONSTRAINTS" -section_id "eda_formal_verification" "ON"
	set_global_assignment -name "EDA_FLATTEN_BUSES" -section_id "eda_palace" "OFF"
	set_global_assignment -name "EDA_GENERATE_FUNCTIONAL_NETLIST" -section_id "eda_palace" "OFF"
	set_global_assignment -name "EDA_RUN_TOOL_AUTOMATICALLY" -section_id "eda_palace" "OFF"
	set_global_assignment -name "EDA_MAINTAIN_DESIGN_HIERARCHY" -section_id "eda_palace" "OFF"
	set_global_assignment -name "EDA_MAP_ILLEGAL_CHARACTERS" -section_id "eda_palace" "OFF"
	set_global_assignment -name "EDA_OUTPUT_DATA_FORMAT" -section_id "eda_palace" "NONE"
	set_global_assignment -name "EDA_TRUNCATE_LONG_HIERARCHY_PATHS" -section_id "eda_palace" "OFF"
	set_global_assignment -name "EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION" -section_id "eda_palace" "OFF"
	set_global_assignment -name "EDA_WRITE_DEVICE_CONTROL_PORTS" -section_id "eda_palace" "OFF"
	set_global_assignment -name "RESYNTHESIS_OPTIMIZATION_EFFORT" -section_id "eda_palace" "NORMAL"
	set_global_assignment -name "RESYNTHESIS_PHYSICAL_SYNTHESIS" -section_id "eda_palace" "NORMAL"
	set_global_assignment -name "RESYNTHESIS_RETIMING" -section_id "eda_palace" "FULL"
	set_global_assignment -name "USE_GENERATED_PHYSICAL_CONSTRAINTS" -section_id "eda_palace" "ON"
	set_global_assignment -name "DIVIDE_BASE_CLOCK_PERIOD_BY" -section_id "CLK_BRD" "1"
	set_global_assignment -name "INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS" -section_id "CLK_BRD" "OFF"
	set_global_assignment -name "INVERT_BASE_CLOCK" -section_id "CLK_BRD" "OFF"
	set_global_assignment -name "MULTIPLY_BASE_CLOCK_PERIOD_BY" -section_id "CLK_BRD" "1"
	set_global_assignment -name "DUTY_CYCLE" -section_id "CLK_BRD" "50"
	set_global_assignment -name "FMAX_REQUIREMENT" -section_id "CLK_BRD" "40.0 MHz"

	# Compiler Assignments for .ReplaceProjectName
	set_project_settings -cmp ".ReplaceProjectName"
	set_global_assignment -name "ADV_NETLIST_OPT_RETIME_CORE_AND_IO" "ON"
	set_global_assignment -name "ADV_NETLIST_OPT_SYNTH_GATE_RETIME" "OFF"
	set_global_assignment -name "ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO" "OFF"
	set_global_assignment -name "ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP" "OFF"
	set_global_assignment -name "COMPILATION_LEVEL" "FULL"
	set_global_assignment -name "DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1" "MEGALAB COLUMN 1"
	set_global_assignment -name "DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1" "MEGALAB COLUMN 1"
	set_global_assignment -name "DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1" "LOWER TO 1ESB UPPER TO 1"
	set_global_assignment -name "DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1" "MEGALAB COLUMN 1"
	set_global_assignment -name "DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1" "MEGALAB COLUMN 1"
	set_global_assignment -name "DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1" "MEGALAB COLUMN 1"
	set_global_assignment -name "DPRAM_DEEP_MODE_INPUT_EPXA4_10" "MEGALAB COLUMN 3"
	set_global_assignment -name "DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10" "MEGALAB COLUMN 3"
	set_global_assignment -name "DPRAM_DEEP_MODE_OUTPUT_EPXA4_10" "MEGALAB COLUMN 3"
	set_global_assignment -name "DPRAM_DUAL_PORT_MODE_INPUT_EPXA1" "DPRAM0 TO 1 DPRAM1 TO 2"
	set_global_assignment -name "DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10" "DPRAM0 TO 3 DPRAM1 TO 4"
	set_global_assignment -name "DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1" "DPRAM0 TO 1 DPRAM1 TO 2"
	set_global_assignment -name "DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10" "DPRAM0 TO 3 DPRAM1 TO 4"
	set_global_assignment -name "DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1" "DPRAM0 TO 1 DPRAM1 TO 2"
	set_global_assignment -name "DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10" "DPRAM0 TO 3 DPRAM1 TO 4ESB"
	set_global_assignment -name "DPRAM_INPUT_EPXA4_10" "DEFAULT INPUT ROUTING OPTIONS"
	set_global_assignment -name "DPRAM_OTHER_SIGNALS_EPXA4_10" "DEFAULT OTHER ROUTING OPTIONS"
	set_global_assignment -name "DPRAM_OUTPUT_EPXA4_10" "DEFAULT OUTPUT ROUTING OPTIONS"
	set_global_assignment -name "DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10" "DPRAM0 TO 3 DPRAM1 TO 4"
	set_global_assignment -name "DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10" "DPRAM0 TO 3 DPRAM1 TO 4"
	set_global_assignment -name "DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10" "DPRAM0 TO 3 DPRAM1 TO 4ESB"
	set_global_assignment -name "DPRAM_WIDE_MODE_INPUT_EPXA4_10" "LOWER TO 3 UPPER TO 4"
	set_global_assignment -name "DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10" "MEGALAB COLUMN 3"
	set_global_assignment -name "DPRAM_WIDE_MODE_OUTPUT_EPXA4_10" "LOWER TO 3 UPPER TO 4ESB"
	set_global_assignment -name "DRC_FANOUT_EXCEEDING" "30"
	set_global_assignment -name "DRC_TOP_FANOUT" "50"
	set_global_assignment -name "DRC_REPORT_FANOUT_EXCEEDING" "OFF"
	set_global_assignment -name "DRC_REPORT_TOP_FANOUT" "OFF"
	set_global_assignment -name "ENABLE_DRC_SETTINGS" "OFF"
	set_global_assignment -name "RUN_DRC_DURING_COMPILATION" "OFF"
	set_global_assignment -name "FAMILY" ".ReplaceDeviceFamilyName"
	set_global_assignment -name "FAST_FIT_COMPILATION" "OFF"
	set_global_assignment -name "FINAL_PLACEMENT_OPTIMIZATION" "AUTOMATICALLY"
	set_global_assignment -name "SEED" "1"
	set_global_assignment -name "IO_PLACEMENT_OPTIMIZATION" "ON"
	set_global_assignment -name "MERGE_HEX_FILE" "OFF"
	set_global_assignment -name "OPTIMIZE_HOLD_TIMING" "IO PATHS AND MINIMUM TPD PATHS"
	set_global_assignment -name "OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING" "ON"
	set_global_assignment -name "PHYSICAL_SYNTHESIS_COMBO_LOGIC" "OFF"
	set_global_assignment -name "PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION" "OFF"
	set_global_assignment -name "PHYSICAL_SYNTHESIS_REGISTER_RETIMING" "OFF"
	set_global_assignment -name "PLD_TO_STRIPE_INTERRUPTS_EPXA4_10" "MEGALAB COLUMN 2"
	set_global_assignment -name "PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10" "MEGALAB COLUMN 2"
	set_global_assignment -name "FOCUS_ENTITY_NAME" "|.ReplaceProjectName"
	set_global_assignment -name "SAVE_DISK_SPACE" "ON"
	set_global_assignment -name "SIGNALPROBE_ALLOW_OVERUSE" "OFF"
	set_global_assignment -name "SIGNALPROBE_DURING_NORMAL_COMPILATION" "OFF"
	set_global_assignment -name "SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES" "OFF"
	set_global_assignment -name "SPEED_DISK_USAGE_TRADEOFF" "NORMAL"
	set_global_assignment -name "STRIPE_TO_PLD_BRIDGE_EPXA4_10" "MEGALAB COLUMN 1"
	set_global_assignment -name "STRIPE_TO_PLD_INTERRUPTS_EPXA4_10" "MEGALAB COLUMN 2"
	set_global_assignment -name "OPTIMIZE_TIMING" ".ReplaceOptimizeTiming"
	set_global_assignment -name "TRUE_WYSIWYG_FLOW" "OFF"
	set_global_assignment -name "LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT" "OFF"
	set_global_assignment -name "AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE" "ON"
	set_global_assignment -name "AUTO_RESTART_CONFIGURATION" "OFF"
	set_global_assignment -name "ENABLE_DEVICE_WIDE_OE" "OFF"
	set_global_assignment -name "ENABLE_DEVICE_WIDE_RESET" "OFF"
	set_global_assignment -name "CONFIGURATION_CLOCK_DIVISOR" "1"
	set_global_assignment -name "CONFIGURATION_CLOCK_FREQUENCY" "10 MHZ"
	set_global_assignment -name "CLOCK_SOURCE" "INTERNAL"
	set_global_assignment -name "COMPRESSION_MODE" "OFF"
	set_global_assignment -name "RESERVE_DATA0_AFTER_CONFIGURATION" "AS INPUT TRI-STATED"
	set_global_assignment -name "RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION" "USE AS REGULAR IO"
	set_global_assignment -name "DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE" "OFF"
	set_global_assignment -name "ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE" "ON"
	set_global_assignment -name "ENABLE_VREFA_PIN" "OFF"
	set_global_assignment -name "ENABLE_VREFB_PIN" "OFF"
	set_global_assignment -name "STRATIX_CONFIG_DEVICE_JTAG_USER_CODE" "FFFFFFFF"
	set_global_assignment -name "EPROM_USE_CHECKSUM_AS_USERCODE" "OFF"

	set_global_assignment -name "GENERATE_CONFIG_HEXOUT_FILE" "ON"
	set_global_assignment -name "GENERATE_CONFIG_ISC_FILE" "OFF"
	set_global_assignment -name "GENERATE_CONFIG_JAM_FILE" "ON"
	set_global_assignment -name "GENERATE_CONFIG_JBC_FILE" "ON"
	set_global_assignment -name "GENERATE_CONFIG_JBC_FILE_COMPRESSED" "ON"
	set_global_assignment -name "GENERATE_CONFIG_SVF_FILE" "ON"

	set_global_assignment -name "GENERATE_HEX_FILE" "ON"
	set_global_assignment -name "GENERATE_ISC_FILE" "OFF"
	set_global_assignment -name "GENERATE_JAM_FILE" "ON"
	set_global_assignment -name "GENERATE_JBC_FILE" "ON"
	set_global_assignment -name "GENERATE_JBC_FILE_COMPRESSED" "ON"
	set_global_assignment -name "GENERATE_RBF_FILE" "ON"
	set_global_assignment -name "GENERATE_SVF_FILE" "ON"
	set_global_assignment -name "GENERATE_TTF_FILE" "ON"

	set_global_assignment -name "HEXOUT_FILE_COUNT_DIRECTION" "UP"
	set_global_assignment -name "HEXOUT_FILE_START_ADDRESS" "0"
	set_global_assignment -name "ENABLE_INIT_DONE_OUTPUT" "OFF"
	set_global_assignment -name "ENABLE_JTAG_BST_SUPPORT" "OFF"
	set_global_assignment -name "MAX7000_ENABLE_JTAG_BST_SUPPORT" "ON"
	set_global_assignment -name "RESERVE_NCEO_AFTER_CONFIGURATION" "USE AS REGULAR IO"
	set_global_assignment -name "RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION" "USE AS REGULAR IO"
	set_global_assignment -name "ON_CHIP_BITSTREAM_DECOMPRESSION" "OFF"
	set_global_assignment -name "CYCLONE_CONFIGURATION_SCHEME" ".ReplaceConfigSchemeValue"
	set_global_assignment -name "STRATIX_CONFIGURATION_SCHEME" ".ReplaceConfigSchemeValue"
	set_global_assignment -name "RESERVE_RDYNBUSY_AFTER_CONFIGURATION" "USE AS REGULAR IO"
	set_global_assignment -name "RELEASE_CLEARS_BEFORE_TRI_STATES" "OFF"
	set_global_assignment -name "RESERVE_ALL_UNUSED_PINS" "AS INPUT TRI-STATED"
	set_global_assignment -name "RESERVE_PIN" "AS INPUT TRI-STATED"
	set_global_assignment -name "RESERVE_ASDO_AFTER_CONFIGURATION" "USE AS REGULAR IO"
	set_global_assignment -name "SECURITY_BIT" "OFF"
	set_global_assignment -name "USER_START_UP_CLOCK" "OFF"
	set_global_assignment -name "STRATIX_UPDATE_MODE" "STANDARD"
	set_global_assignment -name "MAX7000_JTAG_USER_CODE" ".ReplaceUserId"
	set_global_assignment -name "MAX7000S_JTAG_USER_CODE" ".ReplaceUserId"
	set_global_assignment -name "STRATIX_JTAG_USER_CODE" ".ReplaceUserId"
	set_global_assignment -name "USE_CHECKSUM_AS_USERCODE" "OFF"
	set_global_assignment -name "MAX7000_USE_CHECKSUM_AS_USERCODE" "OFF"
	set_global_assignment -name "CYCLONE_CONFIGURATION_DEVICE" ".ReplaceConfigDeviceValue"
	set_global_assignment -name "STRATIX_CONFIGURATION_DEVICE" ".ReplaceConfigDeviceValue"
	set_global_assignment -name "USE_CONFIGURATION_DEVICE" "ON"
	set_global_assignment -name "AUTO_INSERT_SLD_HUB_ENTITY" "ENABLE"
	set_global_assignment -name "HUB_ENTITY_NAME" "SLD_HUB"
	set_global_assignment -name "HUB_INSTANCE_NAME" "SLD_HUB_INST"
	set_global_assignment -name "BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE" "OFF"
	set_global_assignment -name "DEVICE" ".ReplaceDeviceName"
	set_global_assignment -name "DEVICE_FILTER_PACKAGE" "ANY"
	set_global_assignment -name "DEVICE_FILTER_PIN_COUNT" "ANY"
	set_global_assignment -name "DEVICE_FILTER_SPEED_GRADE" "ANY"

        # Pin Assignments go into the compiler settings
        if [file exists .ReplaceProjectName_constraints.tcl] {
            source [file join ".ReplaceProjectName_constraints.tcl"];
        }

        # Extra constraints to go into the compiler settings
        if [file exists .ReplaceProjectName_ConstraintsEx.tcl] {
            source [file join ".ReplaceProjectName_ConstraintsEx.tcl"];
        }


	# Simulator Assignments for .ReplaceProjectName
	set_project_settings -sim ".ReplaceProjectName"
	set_global_assignment -name "ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS" "ON"
	set_global_assignment -name "CHECK_OUTPUTS" "OFF"
	set_global_assignment -name "SIMULATION_COVERAGE" "ON"
	set_global_assignment -name "ESTIMATE_POWER_CONSUMPTION" "OFF"
	set_global_assignment -name "GLITCH_DETECTION" "OFF"
	set_global_assignment -name "GLITCH_INTERVAL" "1NS"
	set_global_assignment -name "POWER_ESTIMATION_START_TIME" "0 NS"
	set_global_assignment -name "SETUP_HOLD_DETECTION" "OFF"
	set_global_assignment -name "SIMULATION_MODE" "TIMING"
	set_global_assignment -name "START_TIME" "0NS"
	set_global_assignment -name "USE_COMPILER_SETTINGS" ".ReplaceProjectName"

	# Software Build Assignments for release
	set_project_settings -swb "release"
	set_global_assignment -name "ARM_CPP_COMMAND_LINE" "\"-O2\""
	set_global_assignment -name "BYTE_ORDER" "LITTLE ENDIAN"
	set_global_assignment -name "DO_POST_BUILD_COMMAND_LINE" "OFF"
	set_global_assignment -name "GNUPRO_ARM_CPP_COMMAND_LINE" "\"-O3 -fomit-frame-pointer\""
	set_global_assignment -name "GNUPRO_NIOS_CPP_COMMAND_LINE" "\"-O3\""
	set_global_assignment -name "OUTPUT_FILE_NAME" "Release\\.ReplaceProjectName.hex"
	set_global_assignment -name "OUTPUT_TYPE" "INTEL HEX"
	set_global_assignment -name "PROCESSOR" "ARM922T"
	set_global_assignment -name "PROGRAMMING_FILE_TYPE" "NO PROGRAMMING FILE"
	set_global_assignment -name "TOOLSET" "CUSTOM BUILD"
	set_global_assignment -name "USE_C_PREPROCESSOR_FOR_GNU_ASM_FILES" "ON"

	# Software Build Assignments for debug
	set_project_settings -swb "debug"
	set_global_assignment -name "ARM_ASM_COMMAND_LINE" "\"-g -keep\""
	set_global_assignment -name "ARM_CPP_COMMAND_LINE" "\"-g -O0\""
	set_global_assignment -name "ASP_ASM_COMMAND_LINE" "\"-g\""
	set_global_assignment -name "BYTE_ORDER" "LITTLE ENDIAN"
	set_global_assignment -name "DO_POST_BUILD_COMMAND_LINE" "OFF"
	set_global_assignment -name "GNUPRO_ARM_ASM_COMMAND_LINE" "\"--gdwarf2 -L\""
	set_global_assignment -name "GNUPRO_ARM_CPP_COMMAND_LINE" "\"-g -O0\""
	set_global_assignment -name "GNUPRO_NIOS_ASM_COMMAND_LINE" "\"--gdwarf2 -L\""
	set_global_assignment -name "GNUPRO_NIOS_CPP_COMMAND_LINE" "\"-g -O0\""
	set_global_assignment -name "OUTPUT_FILE_NAME" "Debug\\.ReplaceProjectName.hex"
	set_global_assignment -name "OUTPUT_TYPE" "INTEL HEX"
	set_global_assignment -name "PROCESSOR" "ARM922T"
	set_global_assignment -name "PROGRAMMING_FILE_TYPE" "NO PROGRAMMING FILE"
	set_global_assignment -name "TOOLSET" "CUSTOM BUILD"
	set_global_assignment -name "USE_C_PREPROCESSOR_FOR_GNU_ASM_FILES" "ON"


        set_global_assignment -name "EDA_LMF_FILE" -section_id "eda_design_synthesis" ".ReplaceLMF"

        # Add a listing of all the macro setting files
        if {$enable_pld_flow} {
          if [file exists .ReplaceProjectName_MacroSettings.tcl] {
            source [file join ".ReplaceProjectName_MacroSettings.tcl"];
          }
        }

        # Add any user constraints
        if [file exists .ReplaceProjectName_UserConstraints.tcl] {
          source [file join ".ReplaceProjectName_UserConstraints.tcl"];
        }

	# Commit assignments
	export_assignments

	# Close project
	if {$need_to_close_project} {
		project_close
	}

        if [file exists .ReplaceProjectName.quartus] { 
            file copy -force .ReplaceProjectName.quartus .ReplaceProjectName.quartus_orig
        }

}




