# Load Quartus II Tcl Project package
# For Altera Quartus II 4.0 and 4.1

package require ::quartus::project

set need_to_close_project 1
set make_assignments 1
set enable_pld_flow .ReplaceEnablePLDFlow

# Check that the right project is open
if {[is_project_open]} {
    if {[string compare $quartus(project) ".ReplaceProjectName"]} {
        puts "Project .ReplaceProjectName is not open"
        set make_assignments 0
    }
} else {
    # Only open if not already open
    if {[project_exists .ReplaceProjectName]} {
        project_open -revision .ReplaceProjectName .ReplaceProjectName
    } else {
        project_new -revision .ReplaceProjectName .ReplaceProjectName
    }
    set need_to_close_project 1
}

file delete -force .ReplaceProjectName.quartus
file delete -force .ReplaceProjectName.qpf
file delete -force .ReplaceProjectName.qsf
file delete -force .ReplaceProjectName.psf
file delete -force .ReplaceProjectName.esf
file delete -force .ReplaceProjectName.csf
file delete -force .ReplaceProjectName.ssf
file delete -force .ReplaceProjectName.fsf
file delete -force db

# Make assignments
if {$make_assignments} {
    # Project Assignments
        
    # Add the top level design file 
    set_global_assignment -name "COMPILER_SETTINGS" ".ReplaceProjectName"

    if [file exists .ReplaceProjectName.edn] {
        set_global_assignment -name "EDIF_FILE" ".ReplaceProjectName.edn"
    } else {
        if [file exists .ReplaceProjectName.vqm] {
            set_global_assignment -name "VQM_FILE" ".ReplaceProjectName.vqm"
        }
    }
    
    # Add a listing of all the HDL source files
    if [file exists .ReplaceProjectName_SourceHDLFiles.tcl] {
         source [file join ".ReplaceProjectName_SourceHDLFiles.tcl"];
    }

    # Add a listing of all the macro files
    if [file exists .ReplaceProjectName_MacroFiles.tcl] {
         source [file join ".ReplaceProjectName_MacroFiles.tcl"];
    }



    set_global_assignment -name TOP_LEVEL_ENTITY ".ReplaceProjectName"

    # Device constraints
    set_global_assignment -name FAMILY                    ".ReplaceDeviceFamilyName"
    set_global_assignment -name DEVICE                    ".ReplaceDeviceName"
    set_global_assignment -name DEVICE_FILTER_PACKAGE     "ANY"
    set_global_assignment -name DEVICE_FILTER_PIN_COUNT   "ANY"
    set_global_assignment -name DEVICE_FILTER_SPEED_GRADE "ANY"

    # Device Configuration Constraints
    set_global_assignment -name .ReplaceConfigSchemeFlag               ".ReplaceConfigSchemeValue"
    set_global_assignment -name .ReplaceConfigDeviceFlag               ".ReplaceConfigDeviceValue"
    set_global_assignment -name USE_CONFIGURATION_DEVICE               "ON"
 #   set_global_assignment -name .ReplaceTCLFamilyName_JTAG_USER_CODE  ".ReplaceUserId"
    set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION        "OFF"
    set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"

    # Device IO Constraints
    set_global_assignment -name RESERVE_PIN                "AS INPUT TRI-STATED"
    set_global_assignment -name RESERVE_ALL_UNUSED_PINS    "AS INPUT TRI-STATED"
    set_global_assignment -name AUTO_RESTART_CONFIGURATION "OFF"

    # Global Optimization Constraints
    set_global_assignment -name .ReplaceOptimizationFlag   ".ReplaceOptimization"
    set_global_assignment -name FITTER_EFFORT              ".ReplaceFitterEffort"
    set_global_assignment -name REMOVE_DUPLICATE_LOGIC       ON

    # Global Mapping Constraints
    set_global_assignment -name AUTO_PACKED_REGISTERS      ".ReplacePackRegisters"

    # Timing Constraints
    set_global_assignment -name OPTIMIZE_TIMING                                  ".ReplaceOptimizeTiming"
    set_global_assignment -name IGNORE_CLOCK_SETTINGS                            ".ReplaceIgnoreClockSettings"
    set_global_assignment -name DO_MIN_ANALYSIS                                  "ON"
    set_global_assignment -name DO_MIN_TIMING                                    "OFF"
    set_global_assignment -name OPTIMIZE_HOLD_TIMING                             "IO PATHS AND MINIMUM TPD PATHS"
    set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING       "ON"

    # Tool Constraints
    set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL        Custom
    set_global_assignment -name EDA_LMF_FILE                           ".ReplaceLMF"  -section_id eda_design_synthesis 
    set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES          "ON"           -section_id eda_design_synthesis
    set_global_assignment -name EDA_INPUT_GND_NAME                     GND            -section_id eda_design_synthesis
    set_global_assignment -name EDA_INPUT_VCC_NAME                     VCC            -section_id eda_design_synthesis
    set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY             OFF            -section_id eda_design_synthesis
    set_global_assignment -name EDA_INPUT_DATA_FORMAT                  EDIF           -section_id eda_design_synthesis

    # Programming file options
    set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE            "ON"
    set_global_assignment -name GENERATE_CONFIG_ISC_FILE               "OFF"
    set_global_assignment -name GENERATE_CONFIG_JAM_FILE               "ON"
    set_global_assignment -name GENERATE_CONFIG_JBC_FILE               "ON"
    set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED    "ON"
    set_global_assignment -name GENERATE_CONFIG_SVF_FILE               "ON"
    set_global_assignment -name GENERATE_HEX_FILE                      "ON"
    set_global_assignment -name GENERATE_ISC_FILE                      "OFF"
    set_global_assignment -name GENERATE_JAM_FILE                      "ON"
    set_global_assignment -name GENERATE_JBC_FILE                      "ON"
    set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED           "ON"
    set_global_assignment -name GENERATE_RBF_FILE                      "ON"
    set_global_assignment -name GENERATE_SVF_FILE                      "ON"
    set_global_assignment -name GENERATE_TTF_FILE                      "ON"

    set_global_assignment -name VHDL_INPUT_VERSION                     "VHDL93"
    set_global_assignment -name VERILOG_INPUT_VERSION                  "VERILOG_2001"

    # Design assistant constraints 
    set_global_assignment -name ENABLE_DRC_SETTINGS                    "ON"


    # Pin Assignments go into the compiler settings
    if [file exists .ReplaceProjectName_constraints.tcl] {
        source [file join ".ReplaceProjectName_constraints.tcl"];
    }

    # Extra constraints to go into the compiler settings
    if [file exists .ReplaceProjectName_ConstraintsEx.tcl] {
        source [file join ".ReplaceProjectName_ConstraintsEx.tcl"];
    }


    # Add a listing of all the macro setting files
    if {$enable_pld_flow} {
      if [file exists .ReplaceProjectName_MacroSettings.tcl] {
        source [file join ".ReplaceProjectName_MacroSettings.tcl"];
      }
    }

    # Add Nios 2 user constraints
    if [file exists nios2_cpu.tcl] {
      source [file join "nios2_cpu.tcl"];
    }

    # Add any user constraints
    if [file exists .ReplaceProjectName_UserConstraints.tcl] {
      source [file join ".ReplaceProjectName_UserConstraints.tcl"];
    }

    # Commit assignments
    export_assignments

    # Close project
    if {$need_to_close_project} {
        project_close
    }    

    if {[file exists .ReplaceProjectName.qpf]} { 
        file copy -force .ReplaceProjectName.qpf .ReplaceProjectName.qpf_orig
    }
}