################################################################################
# Default Script for Lattice ISP Lever map
# You can comment any line using a # character to disable the option
# The .Replace* strings denote stings that will be replaced by the system
# to disable this feature just delete the string and replace it with the
# desired hardcoded value
# Any <value> needs to be udpated manually by the user.  They can be replaced
# with a .Replace* string alternatively.  These values are used for the
# modular design process and are not needed for Altium Designer flows.
################################################################################

################################################################################
# Specifies the architecture of the device to which you will map the design. Not
# needed if you are mapping to the architecture specified in the input .ngd file.
# The -a overrides the architecture specified in the input file.
# Note that this is unnecessary to specify if you use the -p option.
#################################################################################
# -a .ReplaceArchitectureName

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# Specifies the part number for the device. May be used in either of two ways:
#   * Device name only (for example, or3c55).
#   * Part number (for example, or3c55s208) Since the part number specifies both 
#     a device and a package, you need not enter a t option (specifying a
#     package).
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-p .ReplacePartName

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# Specifies the package (e.g., s208, fs256, or bm680) for the device to which
# you will map. Package names are given for devices in the Devices appendix.
################################################################################
-t .ReplacePackageName

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# Specifies the speed (toggle rate) of the part. Applicable speeds are given in
# the Devices appendix.
# If not specified, MAP selects the speed as follows:
#  * If the designs netlist file contains a attribute that defines the device
#     speed, MAP selects the speed specified by the attribute.
#  * If no device speed attribute is specified, MAP uses the default speed.
################################################################################
-s .ReplaceSpeedGradeName

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# Special options for 2CA/2TA (not supported in Altium Designer)
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# (2CA/2TA only) Map to 6-input functions. 
# -k
# (2CA/2TA only) Do not perform logic replication.
# -l
# (2CA/2TA only) Do not remove unused logic.
# -u
# (2CA/2TA only) No register ordering. (Note: for Series 3, register ordering is
# always used.) See register ordering namine conventions in 2CA/2TA section.
# -r

################################################################################
# Allow overmapped NCDs.
################################################################################
.ReplaceAllowOvermappedNCDs -m 

################################################################################
# Use the -hier option to designate hierarchical mapping instead of flat mapping
# With the option designated, MAP will not pack components from different top
# level modules into the same PFU. This affords PAR better placement choices
# through improved logic grouping. Keep the following in mind when using the
# -hier option: 
# The hierarchical mapping option will override signal sharing packing of inputs
# or outputs. 
# SWLs or direct connections have higher priority than -hier option.
# The default is flat mapping, same as in previous releases. In addition, the
# COMP= properties will now have hierarchical paths appended to their data
# strings. This allows the multiple instantiation of blocks with COMP=
# properties to be unique and separate.
################################################################################
# -hier 

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# Optional preference file output. Prevents changing the input preference file. 
################################################################################
# -pr <oprffile[.prf]>

################################################################################
# Series 3 only (not supported by Alitum Designer) 
# By default, MAP tries to implement drive-load LUTs using one of the soft-wired
# lookup table (SWL) connections in the PFU.This significantly reduces routing
# delays, since the PFU SWL has nearly 0 delay. Otherwise, the LUTs must use
# outside routing resources which have larger delays. 
#
# The -swl option turns off this soft-wired LUT feature and also specifies degree
# of Softwire LUT (SWL) usage in the design with a predefined subset of SWL
# patterns ranging from empty set to full set. Currently, there are six different
# SWL pattern sets that are executed: 
#
# -swl 0 - No SWL; most area efficient 
# -swl 1 - Full PFU three-level SWLs, Half PFU two-level SWLs; local area efficient 
# -swl 2 - All above, plus all two-level SWLs; less area efficient
# -swl (3-5) - All above, plus three-level SWLs with 6 or 7 LUT4s; less area efficient 
# -swl (6-8) - All above, plus three-level SWLs with 5 or less LUT4s; less area efficient
# -swl (9-10) - All above, plus extended SWLs with some LUT4s upgraded to LUT5s; least area efficient
#
# Using smaller SWL pattern sets will typically result in denser packing. This
# is especially true when combined with -c option. Due to fragmentation, this
# trade-off is non-linear. Using larger SWL pattern sets results in better
# performance reflected in PAR run times and timing. The default SWL option,
# -swl, is the same as using the -swl 8 option.
################################################################################ 
# -swl <1-10>

################################################################################
# To decrease PAR runtimes after minor changes to logical design, guided mapping
# uses a previously generated .ncd file to "guide" the mapping of the new
# logical design. This is specified using the -g option with the file name of
# guide file. This option is only available for Series 3C/L/T designs. 
# All guidance criteria is based on signal name matching. Topology of
# combinatorial logic is considered when Softwire LUTs (SWLs) exist in the
# guided file.
# Register elements are mapped in two passes. In the first pass, register control
# signals are matched by name exactly. In the second pass, the control signals
# names are not matched. This methodology provides a greater chance of matching
# for registers since control signal names have a tendency to change from
# successive synthesis runs. Other matching considerations are as follows:
# For combinatorial logic, new SWLs are matched from SWLs extracted from the
# guide design.
# All unmatched logic are mapped through the regular mapping process.
# The performance of the guided mapped design can be no better than the original
# A guide report, <design_name>.gpr, gives details of the success guided map had
# in matching with the guide file. 
################################################################################
# -g <guide_file>

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# Output file
################################################################################
-o .ReplaceOutputFile

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# Input file
################################################################################
.ReplaceInputFile

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# Preference file
################################################################################
.ReplacePreferenceFile