#.........................................# Parameters #................#
#
set DESIGN     {.ReplaceProjectName}
set DESIGNFILE ".ReplaceProjectName.ReplaceACTELDesignerDBExt"
#
#.......................................................................#

#
# Open Existing Design
#
if { [catch { open_design $DESIGNFILE } ] } {
    error "Unable to open design : $DESIGNFILE"
}

set isLayoutDone [is_design_state_complete .ReplaceLayoutDoneState]
if { $isLayoutDone == 0 } {
    error "Unable to generate timming report because the place & route wasn't done"
}
 
set isBackannotateDone [is_design_state_complete .ReplaceBackannotateDoneState]
if { $isBackannotateDone == 0 } {
    error "Unable to generate the STAPL file because backannotate wasn't done"
}

#                                                                                                             
# Export STAPL File
#
set format    -format
### set fmtname   "STP"  
set fmtname   "bts_stp" 
set staplname "$DESIGN.ReplaceOutputExtension"

if { [ catch { export $format $fmtname -feature "prog_fpga" $staplname } ] } {
    error "Unable to export STAPL file : $staplname"
}

#
# Save Design
#
save_design $DESIGNFILE

#
# Close Design
#
close_design

return 0
# end of file .ReplaceTCLScriptName
